Debugging sequential circuits using Boolean satisfiability. - Moayad Fahim Ali; Andreas G. Veneris; Alexander Smith 001; Sean Safarpour; Rolf Drechsler; Magdy S. Abadir (ICCAD, 2004)

Post-verification debugging of hierarchical designs. - Moayad Fahim Ali; Sean Safarpour; Andreas G. Veneris; Magdy S. Abadir; Rolf Drechsler (ICCAD, 2005)

Fault diagnosis and logic debugging using Boolean satisfiability. - Alexander Smith 001; Andreas G. Veneris; Moayad Fahim Ali; Anastasios Viglas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)