System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation. - Moaz Mostafa; Mona Safar; M. Watheq El-Kharashi; Mohamed Dessouky (MTV, 2014)

SystemVerilog assertion debugging: A visualization and pattern matching model. - Moaz Mostafa; Mona Safar; M. Watheq El-Kharashi; Mohamed Dessouky (PACRIM, 2015)

A Dynamic Power Reduction Methodology based on Reducing Output Transition Rate. - Moaz Mostafa; Ahmed M. Zaki; M. Watheq El-Kharashi; Mohamed Dessouky (PACRIM, 2019)

A Novel Flow for Reducing Dynamic Power and Conditional Performance Improvement. - Moaz Mostafa; M. Watheq El-Kharashi; Mohamed Dessouky; Ahmed M. Zaki (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)