Efficient fetch mechanism by employing instruction register. - Mochamad Asri (Hot Chips Symposium, 2011)

Rethinking processor instruction fetch: Inefficiencies-cracking mechanism. - Mochamad Asri; Naoki Fujieda; Kenji Kise (ISOCC, 2011)

A reconfigurable ASIP-based approach for high performance image signal processing. - Mochamad Asri; Hsuan-Chun Liao; Tsuyoshi Isshiki; Dongju Li; Hiroaki Kunieda (APCCAS, 2012)

A Reconfigurable High Performance ASIP Engine for Image Signal Processing. - Hsuanchun Liao; Mochamad Asri; Tsuyoshi Isshiki; Dongju Li; Hiroaki Kunieda (IPDPS Workshops, 2012)

A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing. - Hsuan-Chun Liao; Mochamad Asri; Tsuyoshi Isshiki; Dongju Li; Hiroaki Kunieda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine. - Hsuan-Chun Liao; Mochamad Asri; Tsuyoshi Isshiki; Dongju Li; Hiroaki Kunieda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing. - Hsuan-Chun Liao; Mochamad Asri; Tsuyoshi Isshiki; Dongju Li; Hiroaki Kunieda (J. Inf. Process., 2013)

Simulator calibration for accelerator-rich architecture studies. - Mochamad Asri; Ardavan Pedram; Lizy K. John; Andreas Gerstlauer (SAMOS, 2016)

The Non-Uniform Compute Device (NUCD) Architecture for Lightweight Accelerator Offload. - Mochamad Asri; Curtis Dunham; Roxana Rusitoru; Andreas Gerstlauer; Jonathan Beard (PDP, 2020)

Hardware Accelerator Integration Tradeoffs for High-Performance Computing: A Case Study of GEMM Acceleration in N-Body Methods. - Mochamad Asri; Dhairya Malhotra; Jiajun Wang; George Biros; Lizy K. John; Andreas Gerstlauer (IEEE Trans. Parallel Distributed Syst., 2021)

CASPHAr: Cache-Managed Accelerator Staging and Pipelining in Heterogeneous System Architectures. - Mochamad Asri; Andreas Gerstlauer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)