A 20µs turn-on time, 24kHz resolution, 1.5-100MHz digitally programmable temperature-compensated clock generator with 7.5ppm/°C inaccuracy. - Yongxin Li; Nilanjan Pal; Tianyu Wang 006; Mostafa Gamal Ahmed; Ahmed E. AbdelRahman; Mohamed Badr Younis; Ruhao Xia; Kyu-Sang Park; Pavan Kumar Hanumolu (CICC, 2022)

A Carrier-Phase-Recovery Loop for a 3.2pJ/b 24Gb/s QPSK Coherent Optical Receiver. - Ahmed E. AbdelRahman; Mostafa Gamal Ahmed; Mahmoud A. Khalil; Mohamed Badr Younis; Kyu-Sang Park; Pavan Kumar Hanumolu (ISSCC, 2023)

A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop. - Mohamed Badr Younis; Mostafa Gamal Ahmed; Tianyu Wang 006; Ahmed E. AbdelRahman; Mahmoud A. Khalil; Anup P. Jose; Pavan Kumar Hanumolu (VLSI Technology and Circuits, 2023)

A 20-μs Turn-On Time, 24-kHz Resolution, 1.5-100-MHz Digitally Programmable Temperature-Compensated Clock Generator. - Yongxin Li; Nilanjan Pal; Tianyu Wang 006; Mostafa Gamal Ahmed; Ahmed E. AbdelRahman; Mohamed Badr Younis; Kyu-Sang Park; Ruhao Xia; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2023)

7.8 A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-14GHz and -54.4dBc Spurs Under 50mV Supply Noise. - Mahmoud A. Khalil; Mohamed Badr Younis; Ruhao Xia; Ahmed E. AbdelRahman; Tianyu Wang 006; Kyu-Sang Park; Pavan Kumar Hanumolu (ISSCC, 2024)

36.7 A 1.54pJ/b 64Gb/s 16-QAM Intradyne Coherent Optical Receiver in 28nm CMOS. - Ahmed E. AbdelRahman; Mohamed Badr Younis; Mohamed Osama Selim; Mohamed Saad Aly; Mahmoud A. Khalil; Pavan Kumar Hanumolu (ISSCC, 2025)