Mohamed El-Hadedy
Orcid: 0000-0002-3823-0712Affiliations:
- California State Polytechnic University, Department of Electrical and Computer Engineering, Pomona, USA
According to our database1,
Mohamed El-Hadedy
authored at least 33 papers
between 2008 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
-
on github.com
On csauthors.net:
Bibliography
2023
Integr., November, 2023
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
RECO-LFSR: Reconfigurable Low-power Cryptographic processor based on LFSR for Trusted IoT platforms.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
2022
Integr., 2022
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
2021
Proceedings of the IEEE International Symposium on Software Reliability Engineering, 2021
2020
Proceedings of the 19th IEEE International Conference on Machine Learning and Applications, 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2019
IEEE Trans. Computers, 2019
J. Parallel Distributed Comput., 2019
Analysis and Modeling of Collaborative Execution Strategies for Heterogeneous CPU-FPGA Architectures.
Proceedings of the 2019 ACM/SPEC International Conference on Performance Engineering, 2019
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019
2018
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018
2017
Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems.
J. Signal Process. Syst., 2017
Accelerating Weeder: A DNA Motif Search Tool Using the Micron Automata Processor and FPGA.
IEICE Trans. Inf. Syst., 2017
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
PPE-ARX: Area- and power-efficient VLIW programmable processing element for IoT crypto-systems.
Proceedings of the 2017 NASA/ESA Conference on Adaptive Hardware and Systems, 2017
2016
Posting with credibility in Micro-blogging systems using Digital Signatures and Watermarks: A case study on Twitter.
CoRR, 2016
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
2015
Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy, 2015
2014
Proceedings of the Secure IT Systems - 19th Nordic Conference, NordSec 2014, Tromsø, 2014
2012
2011
Proceedings of the Sixth International Conference on Image and Graphics, 2011
Area efficient processing element architecture for compact hash functions systems on VIRTEX5 FPGA platform.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011
2010
IACR Cryptol. ePrint Arch., 2010
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Performance and area efficient transpose memory architecture for high throughput adaptive signal processing systems.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010
Resource-efficient implementation of Blue Midnight Wish-256 hash function on Xilinx FPGA platform.
Proceedings of the Sixth International Conference on Information Assurance and Security, 2010
2009
Low Area Implementation of the Hash Function "Blue Midnight Wish 256" for FPGA Platforms.
Proceedings of the 1st International Conference on Intelligent Networking and Collaborative Systems, 2009
2008
High Performance Implementation of a Public Key Block Cipher - MQQ, for FPGA Platforms.
IACR Cryptol. ePrint Arch., 2008