A 1.3µW 0.0075mm2 neural amplifier and capacitor-integrated electrodes for high density neural implant recording. - Mohamed Elzeftawi; Samuel Beach; Le Wang; Luke Theogarajan (BioCAS, 2012)

10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS. - Ahmed Elkholy; Ahmed Elmallah; Mohamed Elzeftawi; Ken Chang; Pavan Kumar Hanumolu (ISSCC, 2016)

3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET. - Yohan Frans; Scott McLeod; Hiva Hedayati; Mohamed Elzeftawi; Jin Namkoong; Winson Lin; Jay Im; Parag Upadhyaya; Ken Chang (ISSCC, 2016)

A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET. - Yohan Frans; Mohamed Elzeftawi; Hiva Hedayati; Jay Im; Vassili Kireev; Toan Pham; Jaewook Shin; Parag Upadhyaya; Lei Zhou; Santiago Asuncion; Chris Borrelli; Geoff Zhang; et al. (VLSI Circuits, 2016)

A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET. - Yohan Frans; Scott McLeod; Hiva Hedayati; Mohamed Elzeftawi; Jin Namkoong; Winson Lin; Jay Im; Parag Upadhyaya; Ken Chang (IEEE J. Solid State Circuits, 2016)

A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET. - Yohan Frans; Jaewook Shin; Lei Zhou; Parag Upadhyaya; Jay Im; Vassili Kireev; Mohamed Elzeftawi; Hiva Hedayati; Toan Pham; Santiago Asuncion; Chris Borrelli; Geoff Zhang; et al. (IEEE J. Solid State Circuits, 2017)

A 1.5pJ/bit, 5-to-10Gbps Forwarded-Clock I/O with Per-Lane Clock De-Skew in a Low Power 28nm CMOS Process. - Anup P. Jose; Valentin Abramzon; Mohamed Elzeftawi; Michael Wang; Kyunglok Kim; Younghoon Song; Shiva Moballegh; Jalil Kamali; Amir Amirkhany (CICC, 2019)

A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET. - Aida Varzaghani; Bardia Bozorgzadeh; Jack Lam; Ankush Goel; Xiaobin Yuan; Mohamed Elzeftawi; Mehran Izad; Sudipta Sarkar; Alberto Baldisserotto; Seong-Ryong Ryu; Steven Mikes; Jeffrey Hwang; et al. (VLSI Technology and Circuits, 2022)