Reverse-engineering embedded memory controllers through latency-based analysis. - Mohamed Hassan 002; Anirudh M. Kaushik; Hiren D. Patel (RTAS, 2015)

A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems. - Mohamed Hassan 002; Hiren D. Patel; Rodolfo Pellizzoni (RTAS, 2015)

MCXplore: An automated framework for validating memory controller designs. - Mohamed Hassan 002; Hiren D. Patel (DATE, 2016)

Criticality- and Requirement-Aware Bus Arbitration for Multi-Core Mixed Criticality Systems. - Mohamed Hassan 002; Hiren D. Patel (RTAS, 2016)

Predictable Cache Coherence for Multi-core Real-Time Systems. - Mohamed Hassan 002; Anirudh M. Kaushik; Hiren D. Patel (RTAS, 2017)

HourGlass: Predictable Time-based Cache Coherence Protocol for Dual-Critical Multi-Core Systems. - Nivedita Sritharan; Anirudh M. Kaushik; Mohamed Hassan 002; Hiren D. Patel (CoRR, 2017)

PMC: A Requirement-Aware DRAM Controller for Multicore Mixed Criticality Systems. - Mohamed Hassan 002; Hiren D. Patel; Rodolfo Pellizzoni (ACM Trans. Embed. Comput. Syst., 2017)

Predictable Shared Memory Resources for Multi-Core Real-Time Systems. - Mohamed Hassan 002 (2017)

On the Off-Chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option? - Mohamed Hassan 002 (RTSS, 2018)

Heterogeneous MPSoCs for Mixed-Criticality Systems: Challenges and Opportunities. - Mohamed Hassan 002 (IEEE Des. Test, 2018)

MCXplore: Automating the Validation Process of DRAM Memory Controller Designs. - Mohamed Hassan 002; Hiren D. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems. - Mohamed Hassan 002; Rodolfo Pellizzoni (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A Comparative Study of Predictable DRAM Controllers. - Danlu Guo; Mohamed Hassan 002; Rodolfo Pellizzoni; Hiren D. Patel (ACM Trans. Embed. Comput. Syst., 2018)

Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis. - Mohamed Hassan 002; Anirudh M. Kaushik; Hiren D. Patel (ACM Trans. Embed. Comput. Syst., 2018)

Managing DRAM Interference in Mixed Criticality Embedded Systems. - Mohamed Hassan 002 (ICM, 2019)

Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems. - Nivedita Sritharan; Anirudh M. Kaushik; Mohamed Hassan 002; Hiren D. Patel (RTSS, 2019)

Discriminative Coherence: Balancing Performance and Latency Bounds in Data-Sharing Multi-Core Real-Time Systems. - Mohamed Hassan 002 (ECRTS, 2020)

Analysis of Memory-Contention in Heterogeneous COTS MPSoCs. - Mohamed Hassan 002; Rodolfo Pellizzoni (ECRTS, 2020)

DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining. - Reza Mirosanlou; Mohamed Hassan 002; Rodolfo Pellizzoni (RTAS, 2020)

The Best of All Worlds: Improving Predictability at the Performance of Conventional Coherence with No Protocol Modifications. - Salah Hessien; Mohamed Hassan 002 (RTSS, 2020)

MCsim: An Extensible DRAM Memory Controller Simulator. - Reza Mirosanlou; Danlu Guo; Mohamed Hassan 002; Rodolfo Pellizzoni (IEEE Comput. Archit. Lett., 2020)

Reduced latency DRAM for multi-core safety-critical real-time systems. - Mohamed Hassan 002 (Real Time Syst., 2020)

Duetto: Latency Guarantees at Minimal Performance Cost. - Reza Mirosanlou; Mohamed Hassan 002; Rodolfo Pellizzoni (DATE, 2021)

Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP's T2080 Cache Coherence. - Roger Pujol; Hamid Tabani; Jaume Abella 001; Mohamed Hassan 002; Francisco J. Cazorla (DATE, 2021)

Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems. - Kazi Asifuzzaman; Mohamed Abuelala; Mohamed Hassan 002; Francisco J. Cazorla (ICCAD, 2021)

DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance. - Reza Mirosanlou; Mohamed Hassan 002; Rodolfo Pellizzoni (MEMSYS, 2021)

Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems. - Anirudh Mohan Kaushik; Mohamed Hassan 002; Hiren D. Patel (IEEE Trans. Computers, 2021)

Predictably and Efficiently Integrating COTS Cache Coherence in Real-Time Systems. - Mohamed Hossam; Mohamed Hassan 002 (ECRTS, 2022)

Parallelism-Aware High-Performance Cache Coherence with Tight Latency Bounds. - Reza Mirosanlou; Mohamed Hassan 002; Rodolfo Pellizzoni (ECRTS, 2022)

tinyCare: A tinyML-based Low-Cost Continuous Blood Pressure Estimation on the Extreme Edge. - Khaled Ahmed 003; Mohamed Hassan 002 (ICHI, 2022)

A Tight Holistic Memory Latency Bound Through Coordinated Management of Memory Resources. - Shorouk Abdelhalim; Danesh Germchi; Mohamed Hossam; Rodolfo Pellizzoni; Mohamed Hassan 002 (ECRTS, 2023)

Improving Timing-Related Guarantees for Main Memory in Multicore Critical Embedded Systems. - Asier Fernández de Lecea; Mohamed Hassan 002; Enrico Mezzetti; Jaume Abella 001; Francisco J. Cazorla (RTSS, 2023)

Tracking Coherence-Related Contention Delays in Real-Time Multicore Systems. - Roger Pujol; Mohamed Hassan 002; Hamid Tabani; Jaume Abella 001; Francisco Javier Cazorla-Almeida (SAC, 2023)

The Case for tinyML in Healthcare: CNNs for Real-Time On-Edge Blood Pressure Estimation. - Bailian Sun; Safin Bayes; Abdelrhman Mohamed Abotaleb; Mohamed Hassan 002 (SAC, 2023)

PISCOT: A Pipelined Split-Transaction COTS-Coherent Bus for Multi-Core Real-Time Systems. - Salah Hessien; Mohamed Hassan 002 (ACM Trans. Embed. Comput. Syst., 2023)

DISCO: Time-Compositional Cache Coherence for Multi-Core Real-Time Embedded Systems. - Mohamed Hassan 002 (IEEE Trans. Computers, 2023)

Shared Data Kills Real-Time Cache Analysis. How to Resurrect It? - Safin Bayes; Mohamed Hossam; Mohamed Hassan 002 (DATE, 2024)

Event Monitor Validation in High-Integrity Systems. - Roger Pujol; Sergi Vilardell; Enrico Mezzetti; Mohamed Hassan 002; Jaume Abella 001; Francisco J. Cazorla (DSD, 2024)

HW/SW Collaborative Techniques for Accelerating TinyML Inference Time at No Cost. - Bailian Sun; Mohamed Hassan 002 (DSD, 2024)

A Framework for Explainable, Comprehensive, and Customizable Memory-Centric Workloads. - Mohamed Abuelala; Mohamed Hassan 002 (ICCAD, 2024)

Octopus: A Cycle-Accurate Cache System Simulator. - Mohamed Hossam; Salah Hessien; Mohamed Hassan 002 (IEEE Comput. Archit. Lett., 2024)

Criticality and Requirement Aware Heterogeneous Coherence for Mixed Criticality Systems. - Safin Bayes; Mohamed Hassan 002 (DATE, 2025)

On the Time Predictability of AXI4. - Roger Pujol; Jaume Abella 001; Mohamed Hassan 002; Francisco J. Cazorla (SAC, 2025)