12-Gb/s low-power voltage-mode driver for multi-standard serial-link applications. - Mohamed Megahed; Mohamed R. M. Rizk; Sameh A. Ibrahim; Mohamed Dessouky (ICECS, 2016)

FA*IR: A Fair Top-k Ranking Algorithm. - Meike Zehlike; Francesco Bonchi; Carlos Castillo 001; Sara Hajian; Mohamed Megahed; Ricardo Baeza-Yates (CIKM, 2017)

A Sub 1μW Switched Source + Capacitor Architecture Free of Top/Bottom Plate Parasitic Switching Loss Achieving Peak Efficiency of 80.66% at a Regulated 1.8V Output in 180nm. - Mohamed Megahed; Y. Ramadass; Tejasvi Anand (CICC, 2019)

A Switched Capacitor Multiple Input Single Output Energy Harvester (Solar + Piezo) Achieving 74.6% Efficiency With Simultaneous MPPT. - Abhishekh Devaraj; Mohamed Megahed; Yutao Liu; Ashwin Ramachandran; Tejasvi Anand (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS. - Ashwin Ramachandran; Yusang Chun; Mohamed Megahed; Tejasvi Anand (IEEE J. Solid State Circuits, 2020)

A 27 Gb/s 5.39 pJ/bit 8-ary Modulated Wireline Transceiver Using Pulse Width and Amplitude Modulation Achieving 9.5 dB SNR Improvement over PAM-8. - Mohamed Megahed; Yusang Chun; Zhiping Wang; Tejasvi Anand (VLSI Circuits, 2021)

A Machine Learning Inspired Transceiver with ISI-Resilient Data Encoding: Hybrid-Ternary Coding + 2-Tap FFE + CTLE + Feature Extraction and Classification for 44.7dB Channel Loss in 7.3pJ/bit. - Zhiping Wang; Mohamed Megahed; Yusang Chun; Tejasvi Anand (VLSI Circuits, 2021)

A Single-Clock-Phase Sense Amplifier Architecture with 9x Smaller Clock-to-Q Delay Compared to the StrongARM & 6.3dB Lower Noise Compared to Double-Tail. - Xiaohui Lin 012; Mohamed Megahed; Tejasvi Anand (VLSI Technology and Circuits, 2022)

A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS. - Yusang Chun; Mohamed Megahed; Ashwin Ramachandran; Tejasvi Anand (IEEE J. Solid State Circuits, 2022)

Weight Prediction Using the Hybrid Stacked-LSTM Food Selection Model. - Ahmed M. Elshewey; Mahmoud Y. Shams; Zahraa Tarek; Mohamed Megahed; El-Sayed M. El-Kenawy; Mohamed A. El-dosuky (Comput. Syst. Sci. Eng., 2023)

A Sub-μW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS. - Mohamed Megahed; Tejasvi Anand (IEEE J. Solid State Circuits, 2023)

An SNR-Enhanced 8-Ary (SNRE-8) Modulation Technique for Wireline Transceivers Using Pulse Width, Position, and Amplitude Modulation. - Mohamed Megahed; Yusang Chun; Zhiping Wang; Tejasvi Anand (IEEE J. Solid State Circuits, 2024)

7.1 A 212.5Gb/s DSP-Based PAM-4 Transceiver with 50dB Loss Compensation for Large AI System Interconnects in 4nm FinFET. - Ehung Chen; Henry Park; Mohammed Abdullatif; Miguel Gandara; Ahmed ElShater; Amr Khashaba; Shih-Hao Huang; Tsz-Bin Liu; Atharav Atharav; Joonyeong Lee; Qaiser Nehal; Mohamed Megahed; et al. (ISSCC, 2025)