Parallel Regeneration of Interconnections in VLSI & ULSI Circuits. - Mohamed Nekili; Yvon Savaria (ISCAS, 1993)

A Fast Low-Power Driver for Long Interconnections in VLSI Systems. - Mohamed Nekili; Yvon Savaria; Guy Bois (ISCAS, 1994)

Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. - Mohamed Nekili; Guy Bois; Yvon Savaria (IEEE Trans. Very Large Scale Integr. Syst., 1997)

Design of Clock Distribution Networks in Presence of Process Variations. - Mohamed Nekili; Yvon Savaria; Guy Bois (Great Lakes Symposium on VLSI, 1998)

Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI. - Mohamed Nekili; Yvon Savaria; Guy Bois (IEEE J. Solid State Circuits, 1999)

Minimizing process-induced skew using delay tuning. - Mohamed Nekili; Yvon Savaria; Guy Bois (ISCAS (4), 2001)

Variable-segment & variable-driver parallel regeneration techniques for RLC VLSI interconnects. - Falah R. Awwad; Mohamed Nekili (ACM Great Lakes Symposium on VLSI, 2002)

A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications. - Bill Pontikakis; Mohamed Nekili (ISCAS (5), 2002)

Quadratic deferred-merge embedding algorithm for zero skew clock distribution network. - Haydar Saaied; Dhamin Al-Khalili; Asim J. Al-Khalili; Mohamed Nekili (Timing Issues in the Specification and Synthesis of Digital Systems, 2002)

Adaptive wire adjustment for bounded skew Clock Distribution Network. - Haydar Saaied; Dhamin Al-Khalili; Asim J. Al-Khalili; Mohamed Nekili (ASP-DAC, 2003)

Optimal partitioning of globally asychronous locally synchronous processor arrays. - Adhir Upadhyay; Syed Rafay Hasan; Mohamed Nekili (ACM Great Lakes Symposium on VLSI, 2004)

A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms. - Alexandre Landry; Mohamed Nekili; Yvon Savaria (ISCAS (4), 2005)

Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree. - Haydar Saaied; Dhamin Al-Khalili; Asim J. Al-Khalili; Mohamed Nekili (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

On Modeling of Parallel Repeater-Insertion Methodologies for SoC Interconnects. - Falah R. Awwad; Mohamed Nekili; Venkatanarayana Ramachandran; Mohamad Sawan (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A novel theory on parallel repeater-insertion methodologies for long on-chip interconnects. - Falah R. Awwad; Mohamed Nekili; Mohamad Sawan (Int. J. Circuit Theory Appl., 2012)