Fast floorplanning for fixed-outline and nonrectangular regions. - Mohammad A. Ahmed; Shantesh Pinge; Malgorzata Chrzanowska-Jeske (ICECS, 2012)

TSV stress-aware performance and reliability analysis. - Muhammad Ali 006; Mohammad A. Ahmed; Malgorzata Chrzanowska-Jeske (ICECS, 2012)

TSV capacitance aware 3-D floorplanning. - Mohammad A. Ahmed; Malgorzata Chrzanowska-Jeske (3DIC, 2013)

3D floorplanning with nets-to-TSVs assignment. - Mohammad A. Ahmed; Sucheta Mohapatra; Malgorzata Chrzanowska-Jeske (ICECS, 2014)

Stochastic analysis of CNFET circuits using enhanced logical effort model in the presence of metallic tubes. - Muhammad Ali 006; Mohammad A. Ahmed; Malgorzata Chrzanowska-Jeske (ICECS, 2014)

Delay and power optimization with TSV-aware 3D floorplanning. - Mohammad A. Ahmed; Malgorzata Chrzanowska-Jeske (ISQED, 2014)

TSVs in early layout design exploration for 3D ICs. - Mohammad A. Ahmed; Malgorzata Chrzanowska-Jeske (LASCAS, 2014)

Dynamic nets-to-TSVs assignment in 3D floorplanning. - Mohammad A. Ahmed; Sucheta Mohapatra; Malgorzata Chrzanowska-Jeske (ISCAS, 2015)

Buffered Interconnects in 3D IC Layout Design. - Mohammad A. Ahmed; Sucheta Mohapatra; Malgorzata Chrzanowska-Jeske (SLIP, 2016)

Performance optimization and power efficiency in 3D IC with buffer insertion scheme. - Mohammad A. Ahmed; Sucheta Mohapatra; Malgorzata Chrzanowska-Jeske (SoCC, 2016)

Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization. - Muhammad Ali 006; Mohammad A. Ahmed; Malgorzata Chrzanowska-Jeske (IEEE Trans. Very Large Scale Integr. Syst., 2019)