Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture. - Shervin Sharifi; Mohammad Hosseinabady; Pedram A. Riahi; Zainalabedin Navabi (DFT, 2003)

Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing. - Shervin Sharifi; Mohammad Hosseinabady; Zainalabedin Navabi (VLSI-SOC, 2003)

TED+: a data structure for microprocessor verification. - Pejman Lotfi-Kamran; Mohammad Hosseinabady; Hamid Shojaei; Mehran Massoumi; Zainalabedin Navabi (ASP-DAC, 2005)

Simultaneous Reduction of Dynamic and Static Power in Scan Structures. - Shervin Sharifi; Javid Jaffari; Mohammad Hosseinabady; Ali Afzali-Kusha; Zainalabedin Navabi (DATE, 2005)

A Flow Graph Technique for DFT Controller Modification. - Mohammad Hosseinabady; Pejman Lotfi-Kamran; Pedram A. Riahi; Fabrizio Lombardi; Zainalabedin Navabi (SoCC, 2005)

A concurrent testing method for NoC switches. - Mohammad Hosseinabady; Abbas Banaiyan; Mahdi Nazm Bojnordi; Zainalabedin Navabi (DATE, 2006)

Single-Event Upset Analysis and Protection in High Speed Circuits. - Mohammad Hosseinabady; Pejman Lotfi-Kamran; Giorgio Di Natale; Stefano Di Carlo; Alfredo Benso; Paolo Prinetto (ETS, 2006)

Scan-Based Structure with Reduced Static and Dynamic Power Consumption. - Shervin Sharifi; Javid Jaffari; Mohammad Hosseinabady; Ali Afzali-Kusha; Zainalabedin Navabi (J. Low Power Electron., 2006)

Single Event Upset Detection and Correction. - Jawar Singh; Jimson Mathew; Mohammad Hosseinabady; Dhiraj K. Pradhan (ICIT, 2007)

Using the inter- and intra-switch regularity in NoC switch testing. - Mohammad Hosseinabady; Atefe Dalirsani; Zainalabedin Navabi (DATE, 2007)

Reliable network-on-chip based on generalized de Bruijn graph. - Mohammad Hosseinabady; Mohammad Reza Kakoee; Jimson Mathew; Dhiraj K. Pradhan (HLDVT, 2007)

An Analytical Model for Reliability Evaluation of NoC Architectures. - Atefe Dalirsani; Mohammad Hosseinabady; Zainalabedin Navabi (IOLTS, 2007)

Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. - Mohammad Hosseinabady; Mohammad Hossein Neishaburi; Zainalabedin Navabi; Alfredo Benso; Stefano Di Carlo; Paolo Prinetto; Giorgio Di Natale (IOLTS, 2007)

A UML Based System Level Failure Rate Assessment Technique for SoC Designs. - Mohammad Hosseinabady; Mohammad Hossein Neishaburi; Pejman Lotfi-Kamran; Zainalabedin Navabi (VTS, 2007)

Low overhead DFT using CDFG by modifying controller. - Mohammad Hosseinabady; Pejman Lotfi-Kamran; Fabrizio Lombardi; Zainalabedin Navabi (IET Comput. Digit. Tech., 2007)

Low test application time resource binding for behavioral synthesis. - Mohammad Hosseinabady; Pejman Lotfi-Kamran; Zainalabedin Navabi (ACM Trans. Design Autom. Electr. Syst., 2007)

Fault-tolerant dynamically reconfigurable NoC-based SoC. - Mohammad Hosseinabady; José L. Núñez-Yáñez (ASAP, 2008)

De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. - Mohammad Hosseinabady; Mohammad Reza Kakoee; Jimson Mathew; Dhiraj K. Pradhan (DATE, 2008)

Fault tolerant bit parallel finite field multipliers using LDPC codes. - Jimson Mathew; Jawar Singh; Abusaleh M. Jabir; Mohammad Hosseinabady; Dhiraj K. Pradhan (ISCAS, 2008)

A Selective Trigger Scan Architecture for VLSI Testing. - Mohammad Hosseinabady; Shervin Sharifi; Fabrizio Lombardi; Zainalabedin Navabi (IEEE Trans. Computers, 2008)

Energy optimization in a Network-on-Chip with dynamically reconfigurable processing nodes. - José L. Núñez-Yáñez; Mohammad Hosseinabady; Atukem Nabina; Izhar Zaidi (CCA/ISIC, 2009)

Run-time resource management in fault-tolerant network on reconfigurable chips. - Mohammad Hosseinabady; José L. Núñez-Yáñez (FPL, 2009)

SystemC Architectural Transaction Level Modelling for Large NoCs. - Mohammad Hosseinabady; José L. Núñez-Yáñez (FDL, 2010)

Effective modelling of large NoCs using SystemC. - Mohammad Hosseinabady; José L. Núñez-Yáñez (ISCAS, 2010)

Task Dispersal Measurement in Dynamic Reconfigurable NoCs. - Mohammad Hosseinabady; José Luis Núñez-Yáñez; Antonio Marcello Coppola (ISVLSI, 2010)

Single-Event Transient Analysis in High Speed Circuits. - Mohammad Hosseinabady; Pejman Lotfi-Kamran; Jimson Mathew; Saraju P. Mohanty; Dhiraj K. Pradhan (ISED, 2011)

Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph. - Mohammad Hosseinabady; Mohammad Reza Kakoee; Jimson Mathew; Dhiraj K. Pradhan (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Exploring dynamically reconfigurable multicore designs with NoRC designer. - José L. Núñez-Yáñez; Arash Beldachi; Atukem Nabina; Mohammad Hosseinabady (HPCS, 2012)

Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles. - Mohammad Hosseinabady; José Luis Núñez-Yáñez (IET Comput. Digit. Tech., 2012)

Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation. - Mohammad Hosseinabady; José Luis Núñez-Yáñez (IET Comput. Digit. Tech., 2012)

Run-time power gating in hybrid ARM-FPGA devices. - Mohammad Hosseinabady; José Luis Núñez-Yáñez (FPL, 2014)

Energy optimization of FPGA-based stream-oriented computing with power gating. - Mohammad Hosseinabady; José Luis Núñez-Yáñez (FPL, 2015)

Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices. - Mohammad Hosseinabady; José Luis Núñez-Yáñez (FPL, 2015)

Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling. - José Luis Núñez-Yáñez; Mohammad Hosseinabady; Arash Beldachi (IEEE Trans. Computers, 2016)

A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis. - Mohammad Hosseinabady; José Luis Núñez-Yáñez (FPL, 2017)

Pipelined Streaming Computation of Histogram in FPGA OpenCL. - Mohammad Hosseinabady; José Luis Núñez-Yáñez (PARCO, 2017)

Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip. - José L. Núñez-Yáñez; Mohammad Hosseinabady; Andrés Rodríguez 001; Rafael Asenjo; Angeles G. Navarro; Ruben Gran Tejero; Darío Suárez Gracia (PARCO, 2017)

Multi-precision convolutional neural networks on heterogeneous hardware. - Sam Amiri; Mohammad Hosseinabady; Simon McIntosh-Smith; José L. Núñez-Yáñez (DATE, 2018)

Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips. - Sam Amiri; Mohammad Hosseinabady; Andrés Rodríguez 001; Rafael Asenjo; Angeles G. Navarro; José L. Núñez-Yáñez (FPL, 2018)

Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems. - José L. Núñez-Yáñez; Mohammad Hosseinabady; Moslem Amiri; Andrés Rodríguez 001; Rafael Asenjo; Angeles G. Navarro; Ruben Gran Tejero; Darío Suárez Gracia (CoRR, 2018)

Dynamic Energy Management of FPGA Accelerators in Embedded Systems. - Mohammad Hosseinabady; José Luis Núñez-Yáñez (ACM Trans. Embed. Comput. Syst., 2018)

Heterogeneous FPGA+GPU Embedded Systems: Challenges and Opportunities. - Mohammad Hosseinabady; Mohd Amiruddin Bin Zainol; José L. Núñez-Yáñez (CoRR, 2019)

Simultaneous multiprocessing in a software-defined heterogeneous FPGA. - José L. Núñez-Yáñez; Sam Amiri; Mohammad Hosseinabady; Andrés Rodríguez 001; Rafael Asenjo; Angeles G. Navarro; Darío Suárez Gracia; Ruben Gran (J. Supercomput., 2019)

Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA. - José L. Núñez-Yáñez; Sam Amiri; Mohammad Hosseinabady; Andrés Rodríguez 001; Rafael Asenjo; Angeles G. Navarro; Darío Suárez Gracia; Ruben Gran (J. Supercomput., 2019)

Sparse Matrix-Dense Matrix Multiplication on Heterogeneous CPU+FPGA Embedded System. - Mohammad Hosseinabady; José L. Núñez-Yáñez (PARMA-DITAM@HiPEAC, 2020)

Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling. - José L. Núñez-Yáñez; Kris Nikov; Kerstin Eder; Mohammad Hosseinabady (PARMA-DITAM@HiPEAC, 2020)

High-Performance Simultaneous Multiprocessing for Heterogeneous System-on-Chip. - Kris Nikov; Mohammad Hosseinabady; Rafael Asenjo; Andrés Rodríguez 001; Angeles G. Navarro; José L. Núñez-Yáñez (CoRR, 2020)

A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis. - Mohammad Hosseinabady; José Luis Núñez-Yáñez (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Sparse and dense matrix multiplication hardware for heterogeneous multi-precision neural networks. - José L. Núñez-Yáñez; Mohammad Hosseinabady (Array, 2021)