Using Integer Equations for High Level Formal Verification Property Checking. - Bijan Alizadeh; Mohammad Reza Kakoee (ISQED, 2003)

Modified Pseudo LRU Replacement Algorithm. - Hassan Ghasemzadeh 001; Sepideh Mazrouee; Mohammad Reza Kakoee (ECBS, 2006)

Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors. - Mohammad Hossein Neishaburi; Masoud Daneshtalab; Mohammad Reza Kakoee; Saeed Safari (AICCSA, 2007)

A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. - Mohammad Hossein Neishaburi; Mohammad Reza Kakoee; Masoud Daneshtalab; Saeed Safari; Zainalabedin Navabi (DDECS, 2007)

On-Chip Verification of NoCs Using Assertion Processors. - Mohammad Reza Kakoee; Mohammad Hossein Neishaburi; Masoud Daneshtalab; Saeed Safari; Zainalabedin Navabi (DSD, 2007)

Functional Test-Case Generation by a Control Transaction Graph for TLM Verification. - Mohammad Reza Kakoee; Mohammad Hossein Neishaburi; Siamak Mohammadi (DSD, 2007)

Reliable network-on-chip based on generalized de Bruijn graph. - Mohammad Hosseinabady; Mohammad Reza Kakoee; Jimson Mathew; Dhiraj K. Pradhan (HLDVT, 2007)

A New Approach for Design and Verification of Transaction Level Models. - Mohammad Reza Kakoee; Hamid Shojaei; Hassan Ghasemzadeh 001; Marjan Sirjani; Zainalabedin Navabi (ISCAS, 2007)

Assertion based design error diagnosis for core-based SoCs. - Mohammad Reza Kakoee; Mohammad Hossein Neishaburi; Masoud Daneshtalab; Saeed Safari (SoCC, 2007)

HW/SW architecture for soft-error cancellation in real-time operating system. - Mohammad Hossein Neishaburi; Mohammad Reza Kakoee; Masoud Daneshtalab; Saeed Safari (IEICE Electron. Express, 2007)

De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. - Mohammad Hosseinabady; Mohammad Reza Kakoee; Jimson Mathew; Dhiraj K. Pradhan (DATE, 2008)

Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification. - Mohammad Reza Kakoee; Mohammad Riazati; Siamak Mohammadi (DSD, 2008)

Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions. - Mohammad Reza Kakoee; Mohammad Riazati; Siamak Mohammadi (ISQED, 2008)

Graph based test case generation for TLM functional verification. - Mohammad Reza Kakoee; Mohammad Hossein Neishaburi; Siamak Mohammadi (Microprocess. Microsystems, 2008)

A floorplan-aware interactive tool flow for NoC design and synthesis. - Mohammad Reza Kakoee; Federico Angiolini; Srinivasan Murali; Antonio Pullini; Ciprian Seiculescu; Luca Benini (SoCC, 2009)

A new physical routing approach for robust bundled signaling on NoC links. - Mohammad Reza Kakoee; Igor Loi; Luca Benini (ACM Great Lakes Symposium on VLSI, 2010)

Automatic synthesis of near-threshold circuits with fine-grained performance tunability. - Mohammad Reza Kakoee; Ashoka Visweswara Sathanur; Antonio Pullini; Jos Huisken; Luca Benini (ISLPED, 2010)

ReliNoC: A reliable network for priority-based on-chip communication. - Mohammad Reza Kakoee; Valeria Bertacco; Luca Benini (DATE, 2011)

A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters. - Abbas Rahimi; Igor Loi; Mohammad Reza Kakoee; Luca Benini (DATE, 2011)

Moonrake chip - GALS demonstrator in 40 nm CMOS technology. - Milos Krstic; Xin Fan 003; Eckhard Grass; Christoph Heer; Birgit Sanders; Luca Benini; Mohammad Reza Kakoee; Alessandro Strano; Davide Bertozzi (SoC, 2011)

A distributed and topology-agnostic approach for on-line NoC testing. - Mohammad Reza Kakoee; Valeria Bertacco; Luca Benini (NOCS, 2011)

Fine-Grained Power and Body-Bias Control for Near-Threshold Deep Sub-Micron CMOS Circuits. - Mohammad Reza Kakoee; Luca Benini (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph. - Mohammad Hosseinabady; Mohammad Reza Kakoee; Jimson Mathew; Dhiraj K. Pradhan (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A resilient architecture for low latency communication in shared-L1 processor clusters. - Mohammad Reza Kakoee; Igor Loi; Luca Benini (DATE, 2012)

A multi-banked shared-l1 cache architecture for tightly coupled processor clusters. - Mohammad Reza Kakoee; Vladimir Petrovic; Luca Benini (ISSoC, 2012)

A tightly-coupled multi-core cluster with shared-memory HW accelerators. - Masoud Dehyadegari; Andrea Marongiu; Mohammad Reza Kakoee; Luca Benini; Siamak Mohammadi; Nasser Yazdani (ICSAMOS, 2012)

Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience. - Milos Krstic; Xin Fan 003; Eckhard Grass; Luca Benini; Mohammad Reza Kakoee; Christoph Heer; Birgit Sanders; Alessandro Strano; Davide Bertozzi (Int. J. Embed. Real Time Commun. Syst., 2012)

Row-based FBB: A design-time optimization for post-silicon tunable circuits. - Mohammad Reza Kakoee; Ashoka Visweswara Sathanur; Antonio Pullini; Luca Benini (Microelectron. J., 2012)

Robust Near-Threshold Design With Fine-Grained Performance Tunability. - Mohammad Reza Kakoee; Luca Benini (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters. - Mohammad Reza Kakoee; Igor Loi; Luca Benini (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A shared-FPU architecture for ultra-low power MPSoCs. - Mohammad Reza Kakoee; Igor Loi; Luca Benini (Conf. Computing Frontiers, 2013)

At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs. - Mohammad Reza Kakoee; Valeria Bertacco; Luca Benini (IEEE Trans. Computers, 2014)

Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators. - Masoud Dehyadegari; Andrea Marongiu; Mohammad Reza Kakoee; Siamak Mohammadi; Nasser Yazdani; Luca Benini (IEEE Trans. Computers, 2015)