SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems. - Mohammad Shihabul Haque; Andhi Janapsatya; Sri Parameswaran (CODES+ISSS, 2009)

SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. - Mohammad Shihabul Haque; Jorgen Peddersen; Andhi Janapsatya; Sri Parameswaran (DAC, 2010)

DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. - Mohammad Shihabul Haque; Jorgen Peddersen; Andhi Janapsatya; Sri Parameswaran (DATE, 2010)

Rapid runtime estimation methods for pipelined MPSoCs. - Haris Javaid; Andhi Janapsatya; Mohammad Shihabul Haque; Sri Parameswaran (DATE, 2010)

CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique. - Mohammad Shihabul Haque; Jorgen Peddersen; Sri Parameswaran (ICCAD, 2011)

DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs. - Mohammad Shihabul Haque; Roshan G. Ragel; Jude Angelo Ambrose; Swarnalatha Radhakrishnan; Sri Parameswaran (CODES+ISSS, 2012)

TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs. - Mohammad Shihabul Haque; Akash Kumar 001; Yajun Ha; Qiang Wu; Shaobo Luo (ASP-DAC, 2013)

Accelerating non-volatile/hybrid processor cache design space exploration for application specific embedded systems. - Mohammad Shihabul Haque; Ang Li 006; Akash Kumar 001; Qingsong Wei (ASP-DAC, 2015)

A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems. - Mohammad Shihabul Haque; Sriram Vasudevan; Alamuri Sriram Nihar; Arvind Easwaran; Akash Kumar 001; Y. C. Tay (ISORC, 2018)

Contract-Based Hierarchical Resilience Management for Cyber-Physical Systems. - Mohammad Shihabul Haque; Daniel Jun Xian Ng; Arvind Easwaran; Karthikeyan Thangamariappan (Computer, 2018)

Predictability and Performance Aware Replacement Policy PVISAM for Unified Shared Caches in Real-time Multicores. - Mohammad Shihabul Haque; Arvind Easwaran (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)