A 97% Peak Efficiency Single-Inductor-Multiple-Output DC-DC Converter with a Shared Bootstrap Gate Driver. - Mohammadreza Zeinali (CoRR, 2024)

Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation. - Mohammadreza Zeinali; Szu-Yao Hung; Sudhakar Pamarti (IEEE J. Solid State Circuits, 2024)

Corrections to "Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation". - Mohammadreza Zeinali; Sudhakar Pamarti (IEEE J. Solid State Circuits, 2025)