Mohammed Thari Nabeel

Orcid: 0000-0002-3924-7356

Affiliations:
  • New York University Abu Dhabi (NYU Abu Dhabi), Division of Engineering, United Arab Emirates


According to our database1, Mohammed Thari Nabeel authored at least 32 papers between 2017 and 2024.

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Bibliography

2024
NiLoPher: Breaking a Modern SAT-Hardened Logic-Locking Scheme via Power Analysis Attack.
IACR Cryptol. ePrint Arch., 2024

Lightweight Masking Against Static Power Side-Channel Attacks.
CoRR, 2024

2023
RPU: The Ring Processing Unit.
IACR Cryptol. ePrint Arch., 2023

Beware Your Standard Cells! On Their Role in Static Power Side-Channel Attacks.
IACR Cryptol. ePrint Arch., 2023

Optimizing Constrained-Modulus Barrett Multiplier for Power and Flexibility.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

Design Space Exploration of Modular Multipliers for ASIC FHE accelerators.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel Attacks.
Proceedings of the 2023 International Symposium on Physical Design, 2023

Quantifying the Overheads of Modular Multiplication.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

CoFHEE: A Co-processor for Fully Homomorphic Encryption Execution.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
AntiDOTE: Protecting Debug Against Outsourced Test Entities.
IEEE Trans. Emerg. Top. Comput., 2022

Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology.
Integr., 2022

A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL.
Cryptogr., 2022

SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

2021
Technical report: CoPHEE: Co-processor forPartially Homomorphic Encrypted Execution.
IACR Cryptol. ePrint Arch., 2021

Toward Security Closure in the Face of Reliability Effects ICCAD Special Session Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets.
IEEE Trans. Computers, 2020

Power Side-Channel Attacks in Negative Capacitance Transistor.
IEEE Micro, 2020

Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET).
CoRR, 2020

Muon-Ra: Quantum random number generation from cosmic rays.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

2019
CAD-Base: An Attack Vector into the Electronics Supply Chain.
ACM Trans. Design Autom. Electr. Syst., 2019

NIST Post-Quantum Cryptography- A Hardware Evaluation Study.
IACR Cryptol. ePrint Arch., 2019

An Interposer-Based Root of Trust: Seize the Opportunity for Secure System-Level Integration of Untrusted Chiplets.
CoRR, 2019

Power, Area, Speed, and Security (PASS) Trade-Offs of NIST PQC Signature Candidates Using a C to ASIC Design Flow.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access.
Proceedings of the International Conference on Computer-Aided Design, 2019

CoPHEE: Co-processor for Partially Homomorphic Encrypted Execution.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

MixLock: Securing Mixed-Signal Circuits via Logic Locking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
ATPG-based cost-effective, secure logic locking.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Customized locking of IP blocks on a multi-million-gate SoC.
Proceedings of the International Conference on Computer-Aided Design, 2018

2017
Provably-Secure Logic Locking: From Theory To Practice.
Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, 2017


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