Capacitance driven clock mesh synthesis to minimize skew and power dissipation. - John Reuben; V. Mohammed Zackriya; Salma Nashit; Harish M. Kittur (IEICE Electron. Express, 2013)

Selective Match-Line Energizer Content Addressable Memory(SMLE -CAM). - V. Mohammed Zackriya; Harish M. Kittur (CoRR, 2014)

Low Power fractional-n frequency Divider with Improved Resolution. - V. Mohammed Zackriya; John Reuben; Ashim Harsh; Harish M. Kittur (J. Circuits Syst. Comput., 2014)

Low Energy Metric Content Addressable Memory (CAM) with Multi Voltage Matchline Segments. - V. Mohammed Zackriya; Harish M. Kittur (J. Circuits Syst. Comput., 2016)

Precharge-Free, Low-Power Content-Addressable Memory. - V. Mohammed Zackriya; Harish M. Kittur (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Content Addressable Memory - Early Predict and Terminate Precharge of Match-Line. - Mohammed Zackriya V; Harish M. Kittur (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Latch-Based Logic Locking. - Joseph Sweeney; V. Mohammed Zackriya; Samuel Pagliarini; Lawrence T. Pileggi (HOST, 2020)

Logic IP for Low-Cost IC Design in Advanced CMOS Nodes. - Mehmet Meric Isgenc; Mayler G. A. Martins; V. Mohammed Zackriya; Samuel N. Pagliarini; Lawrence T. Pileggi (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Top-down Physical Design of Soft Embedded FPGA Fabrics. - Prashanth Mohan; Oguz Atli; Onur O. Kibar; V. Mohammed Zackriya; Larry T. Pileggi; Ken Mai (FPGA, 2021)