Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell. - Sayeed Ahmad; Mohit Kumar Gupta 001; Naushad Alam; Mohd. Hasan (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits. - Mohit Kumar Gupta 001; Mohd. Hasan (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7. - Mohit Kumar Gupta 001; Pieter Weckx; Stefan Cosemans; Pieter Schuddinck; Rogier Baert; Dmitry Yakimets; Doyoung Jang; Yasser Sherazi; Praveen Raghavan; Alessio Spessot; Anda Mocuta; Wim Dehaene (ESSDERC, 2017)

Dedicated technology threshold voltage tuning for 6T SRAM beyond N7. - Mohit Kumar Gupta 001; Pieter Weckx; Stefan Cosemans; Pieter Schuddinck; Rogier Baert; Doyoung Jang; Yasser Sherazi; Praveen Raghavan; Alessio Spessot; Anda Mocuta; Wim Dehaene (ICICDT, 2017)

Low Leakage Single Bitline 9 T (SB9T) Static Random Access Memory. - Sayeed Ahmad; Mohit Kumar Gupta 001; Naushad Alam; Mohd. Hasan (Microelectron. J., 2017)

CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out. - Abhairaj Singh; Mahdi Zahedi; Taha Shahroodi; Mohit Gupta 004; Anteneh Gebregiorgis; Manu Komalan; Rajiv V. Joshi; Francky Catthoor; Rajendra Bishnoi; Said Hamdioui (AICAS, 2022)

Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications. - Mohit Gupta 004; Manu Perumkunnil; Andrea Fantini; Saeideh Alinezhad Chamazcoti; Woojin Kim; Marie Garcia Bardon; Gouri Sankar Kar; Arnaud Furnémont (ESSDERC, 2022)

A Soft SIMD Based Energy Efficient Computing Microarchitecture. - Pengbo Yu; Alexandre Levisse; Mohit Gupta 004; Timon Evenblij; Giovanni Ansaloni; Francky Catthoor; David Atienza (CoRR, 2022)

Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices. - Tommaso Marinelli; José Ignacio Gómez Pérez; Christian Tenllado; Manu Komalan; Mohit Gupta 004; Francky Catthoor (ACM Trans. Embed. Comput. Syst., 2022)

A 2Mbit Digital in-Memory Computing Matrix-Vector Multiplier for DNN Inference supporting flexible bit precision and matrix size achieving 612 binary TOPS/W. - Mohit Gupta 004; Stefan Cosemans; Peter Debacker; Wim Dehaene (ESSCIRC, 2023)

Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications. - Mohit Kumar Gupta 001; Manu Perumkunnil; Dwaipayan Biswas; Saeideh Alinezhad Chamazcoti; Gouri Sankar Kar; Arnaud Furnémont; Julien Ryckaert (ISCAS, 2023)

Impact of interconnects enhancement on SRAM design beyond 5nm technology node. - Mohit Kumar Gupta 001; Pieter Weckx; Manu Perumkunnil Komalan; Julien Ryckaert (ISCAS, 2023)

Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories. - Saeideh Alinezhad Chamazcoti; Mohit Gupta 004; Hyungrock Oh; Timon Evenblij; Francky Catthoor; Manu Perumkunnil Komalan; Gouri Sankar Kar; Arnaud Furnémont (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Calibrating DRAMPower Model: A Runtime Perspective from Real-System HPC Measurements. - Xinyu Shi; Dina Ali Abdelhamid; Thomas Ilsche; Saeideh Alinezhad Chamazcoti; Timon Evenblij; Mohit Gupta 004; Dwaipayan Biswas; Francky Catthoor (CoRR, 2024)

An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs. - Pengbo Yu; Flavio Ponzina; Alexandre Levisse; Mohit Gupta 004; Dwaipayan Biswas; Giovanni Ansaloni; David Atienza; Francky Catthoor (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers. - Fanfan Meng; Siang-Yun Lee; Odysseas Zografos; Mohit Gupta 004; Van D. Nguyen; Giovanni De Micheli; Sorin Cotofana; Inge Asselberghs; Christoph Adelmann; Gouri Sankar Kar; Sebastien Couet; Florin Ciubotaru (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)