45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker [pseudorandom bit sequence]. - Seongwon Kim; Mohit Kapur; Mounir Meghelli; Alexander V. Rylyakov; Young Hoon Kwark; Daniel J. Friedman (CICC, 2003)

10+ Gb/s 90nm CMOS serial link demo in CBGA package. - Sergey V. Rylov; Scott K. Reynolds; Daniel W. Storaska; Brian A. Floyd; Mohit Kapur; Thomas Zwick; Sudhir M. Gowda; Michael Sorna (CICC, 2004)

10+ gb/s 90-nm CMOS serial link demo in CBGA package. - Sergey V. Rylov; Scott K. Reynolds; Daniel W. Storaska; Brian A. Floyd; Mohit Kapur; Thomas Zwick; Sudhir M. Gowda; Michael Sorna (IEEE J. Solid State Circuits, 2005)

A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation. - Sameh W. Asaad; Ralph Bellofatto; Bernard Brezzo; Chuck Haymes; Mohit Kapur; Benjamin D. Parker; Thomas Roewer; Proshanta Saha; Todd Takken; José A. Tierno (FPGA, 2012)

Efficient in-system RTL verification and debugging using FPGAs (abstract only). - Proshanta Saha; Chuck Haymes; Ralph Bellofatto; Bernard Brezzo; Mohit Kapur; Sameh W. Asaad (FPGA, 2012)

Confidential computing for OpenPOWER. - Guerney D. H. Hunt; Ramachandra Pai; Michael V. Le; Hani Jamjoom; Sukadev Bhattiprolu; Rick Boivie; Laurent Dufour; Brad Frey; Mohit Kapur; Kenneth A. Goldman; Ryan Grimm; Janani Janakirman; et al. (EuroSys, 2021)

Janus: An Experimental Reconfigurable SmartNIC with P4 Programmability and SDN Isolation. - Bharat Sukhwani; Mohit Kapur; Alda Ohmacht; Liran Schour; Martin Ohmacht; Chris Ward; Chuck Haymes; Sameh W. Asaad (FPGA, 2023)

Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures. - Joseph Zuckerman; John-David Wellman; Ajay Vanamali; Manish Shankar; Gabriele Tombesi; Karthik Swaminathan; Kevin Lee; Mohit Kapur; Robert Philhower; Pradip Bose; Luca P. Carloni (CoRR, 2024)