Lateral silicon nanowire based standard cell design for higher performance. - Om. Prakash; Mohit Sharma 003; Anand Bulusu; A. K. Saxena; S. K. Manhas; Satish Maheshwaram (APCCAS, 2016)

A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation. - Om. Prakash; Satish Maheshwaram; Mohit Sharma 003; Anand Bulusu; A. K. Saxena; S. K. Manhas (VDAT, 2016)

Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance. - Satish Maheshwaram; Om. Prakash; Mohit Sharma 003; Anand Bulusu; Sanjeev Manhas (VDAT, 2017)