Step response analysis of third order OpAmps With slew-rate. - Mohsen Hassanpourghadi; Mohammad Sharifkhani (VLSI-SoC, 2013)

Fast Static Characterization of Residual-Based ADCs. - Mohsen Hassanpourghadi; Mohammad Sharifkhani (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A low-power low-offset dynamic comparator for analog to digital converters. - Mohsen Hassanpourghadi; Milad Zamani; Mohammad Sharifkhani (Microelectron. J., 2014)

A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS. - Jae-Won Nam; Mohsen Hassanpourghadi; Aoyang Zhang; Mike Shuo-Wei Chen (VLSI Circuits, 2016)

A 6-b, 800-MS/s, 3.62-mW Nyquist Rate AC-Coupled VCO-Based ADC in 65-nm CMOS. - Mohsen Hassanpourghadi; Praveen Kumar Sharma; Mike Shuo-Wei Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation. - Jae-Won Nam; Mohsen Hassanpourghadi; Aoyang Zhang; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2018)

A 2-way 7.3-bit 10 GS/s Time-based Folding ADC with Passive Pulse-Shrinking Cells. - Mohsen Hassanpourghadi; Mike Shuo-Wei Chen (CICC, 2019)

Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling. - Juzheng Liu; Mohsen Hassanpourghadi; Qiaochu Zhang; Shiyu Su; Mike Shuo-Wei Chen (ICCAD, 2020)

Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling. - Mohsen Hassanpourghadi; Shiyu Su; Rezwan A. Rasul; Juzheng Liu; Qiaochu Zhang; Mike Shuo-Wei Chen (DAC, 2021)

From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. - Juzheng Liu; Shiyu Su; Meghna Madhusudan; Mohsen Hassanpourghadi; Samuel Saunders; Qiaochu Zhang; Rezwan A. Rasul; Yaguang Li; Jiang Hu; Arvind Kumar Sharma; Sachin S. Sapatnekar; Ramesh Harjani; et al. (ICCAD, 2021)

A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis. - Mohsen Hassanpourghadi; Rezwan A. Rasul; Mike Shuo-Wei Chen (ACM Trans. Design Autom. Electr. Syst., 2021)

Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. - Shiyu Su; Qiaochu Zhang; Mohsen Hassanpourghadi; Juzheng Liu; Rezwan A. Rasul; Mike Shuo-Wei Chen (ASP-DAC, 2022)

TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. - Shiyu Su; Qiaochu Zhang; Juzheng Liu; Mohsen Hassanpourghadi; Rezwan A. Rasul; Mike Shuo-Wei Chen (ASP-DAC, 2022)

A 10GS/s 8b 25fJ/c-s 2850um2 Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology. - Juzheng Liu; Mohsen Hassanpourghadi; Mike Shuo-Wei Chen (ISSCC, 2022)

A 10-GS/s 8-bit 2850-μm2 Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC. - Juzheng Liu; Mohsen Hassanpourghadi; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2022)

A Novel Multi-Objective Optimization Framework for Analog Circuit Customization. - Mutian Zhu; Mohsen Hassanpourghadi; Qiaochu Zhang; Mike Shuo-Wei Chen; Anthony F. J. Levi; Sandeep Gupta 001 (DATE, 2024)

18.4 A 200GS/s 8b 20fJ/c-s Receiver with >60GHz AFE Bandwidth for 800Gb/s Optical Coherent Communications in 5nm FinFET. - R. L. Nguyen; A. Mellati; A. Fernandez; A. Iyer; A. Fan; Benjamín T. Reyes; Cindra Abidin; Claudio Nani; D. Albano; F. Ahmad; Fredy Solis; Gabriele Minoia; et al. (ISSCC, 2024)