Simulation Environment Based on SystemC and VEOS for Multi-core Processors with Virtual AUTOSAR ECUs. - Moisés Urbina; Zaher Owda; Roman Obermaisser (CIT/IUCC/DASC/PICom, 2015)

Multi-core architecture for AUTOSAR based on virtual Electronic Control Units. - Moisés Urbina; Roman Obermaisser (ETFA, 2015)

Hierarchical Transactional Memory Protocol for Distributed Mixed-Criticality Embedded Systems. - Zaher Owda; Moisés Urbina; Roman Obermaisser; Mohammed Abuteir (DASC/PiCom/DataCom/CyberSciTech, 2016)

Co-simulation framework for AUTOSAR multi-core processors with message-based Network-on-Chips. - Moisés Urbina; Hamidreza Ahmadian; Roman Obermaisser (INDIN, 2016)

Efficient Multi-core AUTOSAR-Platform Based on an Input/Output Gateway Core. - Moisés Urbina; Roman Obermaisser (PDP, 2017)

A time-triggered message-based multi-core architecture for AUTOSAR: student research abstract. - Moisés Urbina (SAC, 2017)

Evaluation of Performance and Fault Containment in AUTOSAR Micro-ECUs on a Multi-Core Processor. - Moisés Urbina; Roman Obermaisser (MCSoC, 2018)

TIMEA: Time-triggered message-based multicore architecture for AUTOSAR. - Moisés Ignacio Urbina Fuentes (2020)

AUTOSAR University Package Classic Platform. - Paolo Gai; Moisés Urbina; Errico Guidieri; Giuseppe Serano; Nicola Serreli (ETFA, 2022)