A low latency and area efficient FFT processor for massive MIMO systems. - Mojtaba Mahdavi 001; Ove Edfors; Viktor Öwall; Liang Liu 002 (ISCAS, 2017)

A 38 pJ/b Optimal Soft-MIMO Detector. - Mahdi Shabany; R. Doostnejad; Mojtaba Mahdavi 001; P. Glenn Gulak (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A Low Complexity Massive MIMO Detection Scheme Using Angular-Domain Processing. - Mojtaba Mahdavi 001; Ove Edfors; Viktor Öwall; Liang Liu 002 (GlobalSIP, 2018)

A 70 pJ/b configurable 64-QAM soft MIMO detector. - Mahdi Shabany; Dimpesh Patel; Mario Milicevic; Mojtaba Mahdavi 001; P. Glenn Gulak (Integr., 2018)

A VLSI Implementation of Angular-Domain Massive MIMO Detection. - Mojtaba Mahdavi 001; Ove Edfors; Viktor Öwall; Liang Liu 002 (ISCAS, 2019)

A Low Latency FFT/IFFT Architecture for Massive MIMO Systems Utilizing OFDM Guard Bands. - Mojtaba Mahdavi 001; Ove Edfors; Viktor Öwall; Liang Liu 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Angular-Domain Massive MIMO Detection: Algorithm, Implementation, and Design Tradeoffs. - Mojtaba Mahdavi 001; Ove Edfors; Viktor Öwall; Liang Liu 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Towards Fully Pipelined Decoding of Spatially Coupled Serially Concatenated Codes. - Mojtaba Mahdavi 001; Liang Liu 002; Ove Edfors; Michael Lentmaier; Norbert Wehn; Stefan Weithoffer (ISTC, 2021)

The Effect of Coupling Memory and Block Length on Spatially Coupled Serially Concatenated Codes. - Mojtaba Mahdavi 001; Muhammad Umar Farooq 001; Liang Liu 002; Ove Edfors; Viktor Öwall; Michael Lentmaier (VTC Spring, 2021)

Baseband Processing for 5G and Beyond: Algorithms, VLSI Architectures, and Co-design. - Mojtaba Mahdavi 001 (2021)

Spatially Coupled Serially Concatenated Codes: Performance Evaluation and VLSI Design Tradeoffs. - Mojtaba Mahdavi 001; Stefan Weithoffer; Matthias Herrmann; Liang Liu 002; Ove Edfors; Norbert Wehn; Michael Lentmaier (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Novel Memristive-Based Data Reordering Scheme. - Mojtaba Mahdavi 001 (DSD, 2023)

Towards Low-Complexity, Fully Parallel and Flexible Hardware Realization of DCT/IDCT. - Mojtaba Mahdavi 001 (ICSPCS, 2023)

Fully Parallel, Flexible, and Conflict-Free Interleaver Design using Processing in Memory. - Mojtaba Mahdavi 001 (NEWCAS, 2023)

Reordering-Less FFT: A Novel FFT Processor with Parallel Input/Output in Normal Order. - Mojtaba Mahdavi 001 (SoftCOM, 2023)

Fully Parallel and Reconfigurable Realization of DFT/IDFT using In-Memory Computing. - Mojtaba Mahdavi 001 (WINCOM, 2023)

Towards Low-Complexity Hardware Realization of Adaptive Filters. - Mojtaba Mahdavi 001 (BlackSeaCom, 2024)

Memristor-Based Square Root Computation for Signal Processing Applications. - Mojtaba Mahdavi 001 (BlackSeaCom, 2024)

Multidimensional Euclidean Distance Calculation using In-Memory Computing. - Mojtaba Mahdavi 001 (CITS, 2024)

Efficient Hardware Acceleration of Mean Squared Error Calculation Through In-Memory Computing. - Mojtaba Mahdavi 001 (COINS, 2024)

Reconfigurable Band-Stop Filter Design using Computing In Memory. - Mojtaba Mahdavi 001 (SmartGridComm, 2024)

Hardware Realization of Vector and Matrix Norm Calculation for Signal Processing Applications. - Mojtaba Mahdavi 001 (WINCOM, 2024)

Channel Estimation using Processing In Memory Based on System Identification Technique. - Mojtaba Mahdavi 001 (WINCOM, 2024)