Application of a redefinable symbolic simulation technique in VLSI testability design rules checking. - Mokhtar Hirech; Olivier Florent; Alain Greiner; El Housseine Rejouan (Annual Simulation Symposium, 1994)

A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking. - Mokhtar Hirech; Olivier Florent; Alain Greiner; El Housseine Rejouan (EDAC-ETC-EUROASIC, 1994)

A new approach to scan chain reordering using physical design information. - Mokhtar Hirech; James Beausang; Xinli Gu (ITC, 1998)

Test-model based hierarchical DFT synthesis. - Sanjay Ramnath; Frederic Neuveux; Mokhtar Hirech; Felix Ng (ICCAD, 2002)

Power and Design for Test: A Design Automation Perspective. - Aurelia De Colle; Sanjay Ramnath; Mokhtar Hirech; Subramanian Chebiyam (J. Low Power Electron., 2005)

Test Strategies for Low-Power Devices. - C. P. Ravikumar; Mokhtar Hirech; Xiaoqing Wen (J. Low Power Electron., 2008)

Test cost and test power conflicts: EDA perspective. - Mokhtar Hirech (VTS, 2010)