A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application. - Monalisa Das; Alak Majumder; Abir J. Mondal; Bidyut K. Bhattacharyya (iNIS, 2017)

Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication. - Alak Majumder; Monalisa Das; Suraj Kumar Saw; Abir J. Mondal; Bidyut K. Bhattacharyya (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Hardware Design of Optimized Large Integer Schoolbook Polynomial Multiplications on FPGA. - Monalisa Das; Babita Jajodia (ISOCC, 2022)

FPGA Implementation of Hybrid Karatsuba Multiplications for NIST Post-Quantum Cryptographic Hardware Primitives. - Monalisa Das; Babita Jajodia (ISOCC, 2022)

Area and Delay Trade-Offs in Three-Way Toom-Cook Large Integer Multipliers Implemented on FPGAs. - Monalisa Das; Babita Jajodia (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

ATP-Optimized Implementation of Four-Way Toom-Cook Multiplications on FPGAs for Large Integer Arithmetic. - Monalisa Das; Babita Jajodia (Circuits Syst. Signal Process., 2025)