A single-chip universal digital satellite receiver with 480-MHz IF input. - Alan Y. Kwentus; Patrick Pai; Steven Jaffe; Ray Gomez; Shauhyuarn Sean Tsai; Tom Kwan; Hing T. Hung; Young J. Shin; Vin Hue; Darwin Cheung; Raheel A. Khan; Christopher M. Ward; et al. (IEEE J. Solid State Circuits, 1999)

Reconfigurable Platform for Content Science Research. - Chi-Sheng Shih 001; Chia-Lin Yang; Mong-Kai Ku; Tei-Wei Kuo; Shao-Yi Chien; Yao-Wen Chang; Liang-Gee Chen (RTCSA, 2005)

3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design. - Shao-Yi Chien; Chi-Sheng Shih 001; Mong-Kai Ku; Chia-Lin Yang; Yao-Wen Chang; Tei-Wei Kuo; Liang-Gee Chen (ICME, 2007)

A High Throughput H-QC LDPC Decoder. - Yi-Hsing Chien; Mong-Kai Ku (ISCAS, 2007)

Efficient encoding for dual-diagonal structured LDPC codes based on parity bit prediction and correction. - Chia-Yu Lin; Chih-Chun Wei; Mong-Kai Ku (APCCAS, 2008)

Switching activity reducing layered decoding algorithm for LDPC codes. - Shu-Cheng Chou; Mong-Kai Ku; Chia-Yu Lin (ISCAS, 2008)

Long Length LDPC Code Construction and the Corresponding Decoder Implementation with Adjustable Parallelism. - Chia-Yu Lin; Mong-Kai Ku; Yi-Hsing Chien (VTC Spring, 2008)

Node Operation Reduced Decoding for LDPC Codes. - Chia-Yu Lin; Mong-Kai Ku (ISCAS, 2009)

Support vector machine FPGA implementation for video shot boundary detection application. - Chun F. Hsu; Mong-Kai Ku; Li-Yen Liu (SoCC, 2009)

Two-Way Parity Bit Correction Encoding Algorithm for Dual-Diagonal LDPC Codes. - Chia-Yu Lin; Chih-Chun Wei; Mong-Kai Ku (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Operation reduced low-density parity-check decoding algorithms for low power communication systems. - Chia-Yu Lin; Shu-Cheng Chou; Mong-Kai Ku (Int. J. Commun. Syst., 2013)