Monica Magalhães Pereira

Orcid: 0000-0002-6580-1250

According to our database1, Monica Magalhães Pereira authored at least 28 papers between 2006 and 2023.

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Bibliography

2023
Using evolutionary metaheuristics to solve the mapping and routing problem in networks on chip.
Des. Autom. Embed. Syst., June, 2023

2021
Using Machine Learning to Estimate Latency and Delivered Packets in Hybrids NoCs.
Proceedings of the XI Brazilian Symposium on Computing Systems Engineering, 2021

2020
A Routing based Genetic Algorithm for Task Mapping on MPSoC.
Proceedings of the X Brazilian Symposium on Computing Systems Engineering, 2020

Mapping Wired Links in a Hybrid Wired-Wireless Network-on-Chip.
Proceedings of the X Brazilian Symposium on Computing Systems Engineering, 2020

A Management Technique for Concurrent Access to a Reconfigurable Accelerator.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

A Machine Learning Approach to Accelerating DSE of Reconfigurable Accelerator Systems.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

Regression Ensembles for Fast Design Space Exploration of Heterogeneous Hardware Designs.
Proceedings of the 19th IEEE International Conference on Machine Learning and Applications, 2020

2019
An investigation of latency prediction for NoC-based communication architectures using machine learning techniques.
J. Supercomput., 2019

A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant Nanoscale Design.
Trans. High Perform. Embed. Archit. Compil., 2019

Communication Latency Evaluation on a Software-Defined Network-on-Chip.
Proceedings of the IX Brazilian Symposium on Computing Systems Engineering, 2019

Generating Optimized Multicore Accelerator Architectures.
Proceedings of the IX Brazilian Symposium on Computing Systems Engineering, 2019

Generation of Application Specific Fault Tolerant Irregular NoC Topologies Using Tabu Search.
Proceedings of the IX Brazilian Symposium on Computing Systems Engineering, 2019

A Runtime Power-Aware Phase Predictor for CGRAs.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

2018
ISA-DTMR: Selective Protection in Configurable Heterogeneous Multicores.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2016
A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility.
J. Signal Process. Syst., 2016

Design Space Exploration Using UTNoCs and Genetic Algorithm.
Proceedings of the VI Brazilian Symposium on Computing Systems Engineering, 2016

A Runtime Mapping Algorithm to Tolerate Permanent Faults in a CGRA.
Proceedings of the VI Brazilian Symposium on Computing Systems Engineering, 2016

2015
Enabling NoC Performance Improvement Using a Fault Tolerance Mechanism.
Proceedings of the 2015 Brazilian Symposium on Computing Systems Engineering, 2015

2014
A run-time modulo scheduling by using a binary translation mechanism.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

2013
A just-in-time modulo scheduling for virtual coarse-grained reconfigurable architectures.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

2011
Dynamic Reconfigurable Computing: The Alternative to Homogeneous Multicores under Massive Defect Rates.
Int. J. Reconfigurable Comput., 2011

An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture.
Proceedings of the 14th International Conference on Compilers, 2011

Run-time resource instantiation for fault tolerance in FPGAs.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2009
Adaptive Processing Architectures for the Ultimate Scaling of the CMOS World.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Dynamically Adapted Low-Energy Fault Tolerant Processors.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

2008
Using traditional loop unrolling to fit application on a new hybrid reconfigurable architecture.
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

2007
RoSA: a reconfigurable stream-based architecture.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

2006
Implementation of a HDTV transport stream multiplexer based on ITU-T H.222.0 recommendation.
Proceedings of the 11th Brazilian Symposium on Multimedia and the Web, 2006


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