Impact of inductive integrated voltage regulator on the power attack vulnerability of encryption engines: A simulation study. - Monodeep Kar; Denny Lie; Marilyn Wolf; Vivek De; Saibal Mukhopadhyay (CICC, 2014)

Impact of process variation in inductive integrated voltage regulator on delay and power of digital circuits. - Monodeep Kar; Sergio Carlo; Harish Kumar Krishnamurthy; Saibal Mukhopadhyay (ISLPED, 2014)

Exploring power attack protection of resource constrained encryption engines using integrated low-drop-out regulators. - Arvind Singh; Monodeep Kar; Jong Hwan Ko; Saibal Mukhopadhyay (ISLPED, 2015)

(Invited paper) energy delivery for self-powered IoT devices. - Khondker Zakir Ahmed 001; Monodeep Kar; Saibal Mukhopadhyay (ASP-DAC, 2016)

An integrated inductive VR with a 250MHz all-digital multisampled compensator and on-chip auto-tuning of coefficients in 130nm CMOS. - Monodeep Kar; Arvind Singh; Anand Rajan; Vivek De; Saibal Mukhopadhyay (ESSCIRC, 2016)

Integrated all-digital low-dropout regulator as a countermeasure to power attack in encryption engines. - Arvind Singh; Monodeep Kar; Anand Rajan; Vivek De; Saibal Mukhopadhyay (HOST, 2016)

What does ultra low power requirements mean for side-channel secure cryptography? - Monodeep Kar; Arvind Singh; Anand Rajan; Vivek De; Saibal Mukhopadhyay (ICCD, 2016)

Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines. - Monodeep Kar; Arvind Singh; Sanu Mathew; Anand Rajan; Vivek De; Saibal Mukhopadhyay (ISLPED, 2016)

Improved power side channel attack resistance of a 128-bit AES engine with random fast voltage dithering. - Arvind Singh; Monodeep Kar; Sanu Mathew; Anand Rajan; Vivek De; Saibal Mukhopadhyay (ESSCIRC, 2017)

A case for low frequency single cycle multi hop NoCs for energy efficiency and high performance. - Monodeep Kar; Tushar Krishna (ICCAD, 2017)

Invited paper: Low power requirements and side-channel protection of encryption engines: Challenges and opportunities. - Monodeep Kar; Arvind Singh; Sanu Mathew; Anand Rajan; Vivek De; Saibal Mukhopadhyay (ISLPED, 2017)

8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator. - Monodeep Kar; Arvind Singh; Sanu Mathew; Anand Rajan; Vivek De; Saibal Mukhopadhyay (ISSCC, 2017)

Reducing Side-Channel Leakage of Encryption Engines Using Integrated Low-Dropout Voltage Regulators. - Arvind Singh; Monodeep Kar; Sanu Mathew; Anand Rajan; Vivek De; Saibal Mukhopadhyay (J. Hardw. Syst. Secur., 2017)

An All-Digital Fully Integrated Inductive Buck Regulator With A 250-MHz Multi-Sampled Compensator and a Lightweight Auto-Tuner in 130-nm CMOS. - Monodeep Kar; Arvind Singh; Anand Rajan; Vivek De; Saibal Mukhopadhyay (IEEE J. Solid State Circuits, 2017)

Performance based tuning of an inductive integrated voltage regulator driving a digital core against process and passive variations. - Venakata Chaitanya Krishna Chekuri; Monodeep Kar; Arvind Singh; Saibal Mukhopadhyay (DATE, 2018)

Exploiting on-chip power management for side-channel security. - Arvind Singh; Monodeep Kar; Sanu Mathew; Anand Rajan; Vivek De; Saibal Mukhopadhyay (DATE, 2018)

Energy efficient and side-channel secure hardware architecture for lightweight cipher SIMON. - Arvind Singh; Nikhil Chawla; Monodeep Kar; Saibal Mukhopadhyay (HOST, 2018)

Blindsight: Blinding EM Side-Channel Leakage using Built-In Fully Integrated Inductive Voltage Regulator. - Monodeep Kar; Arvind Singh; Sanu Mathew; Santosh Ghosh; Anand Rajan; Vivek De; Raheem A. Beyah; Saibal Mukhopadhyay (CoRR, 2018)

Reducing Power Side-Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator. - Monodeep Kar; Arvind Singh; Sanu K. Mathew; Anand Rajan; Vivek De; Saibal Mukhopadhyay (IEEE J. Solid State Circuits, 2018)

Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines. - Monodeep Kar (2018)

A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS. - Amit Agarwal 001; Steven Hsu; Monodeep Kar; Mark A. Anders 001; Himanshu Kaul; Raghavan Kumar; Vikram B. Suresh; Sanu Mathew; Ram Krishnamurthy 001; Vivek De (A-SSCC, 2019)

Mitigating Power Supply Glitch based Fault Attacks with Fast All-Digital Clock Modulation Circuit. - Arvind Singh; Monodeep Kar; Nikhil Chawla; Saibal Mukhopadhyay (DATE, 2019)

Extracting Side-Channel Leakage from Round Unrolled Implementations of Lightweight Ciphers. - Nikhil Chawla; Arvind Singh; Nael Mizanur Rahman; Monodeep Kar; Saibal Mukhopadhyay (HOST, 2019)

Application Inference using Machine Learning based Side Channel Analysis. - Nikhil Chawla; Arvind Singh; Monodeep Kar; Saibal Mukhopadhyay (IJCNN, 2019)

A 128b AES Engine with Higher Resistance to Power and Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low-Dropout Regulator. - Arvind Singh; Monodeep Kar; Sanu Mathew; Anand Rajan; Vivek De; Saibal Mukhopadhyay (ISSCC, 2019)

A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS. - Steven Hsu; Amit Agarwal 001; Monodeep Kar; Mark A. Anders 001; Himanshu Kaul; Raghavan Kumar; Sudhir Satpathy; Vikram B. Suresh; Sanu Mathew; Ram Krishnamurthy 001; Vivek De (VLSI Circuits, 2019)

A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition. - Raghavan Kumar; Vikram B. Suresh; Monodeep Kar; Sudhir Satpathy; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram Krishnamurthy 001; Vivek De; Sanu Mathew (VLSI Circuits, 2019)

Multigated Carbon Nanotube Field Effect Transistors-Based Physically Unclonable Functions As Security Keys. - Nitish Kumar; Jialuo Chen; Monodeep Kar; Suresh K. Sitaraman; Saibal Mukhopadhyay; Satish Kumar (IEEE Internet Things J., 2019)

Energy Efficient and Side-Channel Secure Cryptographic Hardware for IoT-Edge Nodes. - Arvind Singh; Nikhil Chawla; Jong Hwan Ko; Monodeep Kar; Saibal Mukhopadhyay (IEEE Internet Things J., 2019)

Improved Power/EM Side-Channel Attack Resistance of 128-Bit AES Engines With Random Fast Voltage Dithering. - Arvind Singh; Monodeep Kar; Sanu K. Mathew; Anand Rajan; Vivek De; Saibal Mukhopadhyay (IEEE J. Solid State Circuits, 2019)

Autotuning of Integrated Inductive Voltage Regulator Using On-Chip Delay Sensor to Tolerate Process and Passive Variations. - Venkata Chaitanya Krishna Chekuri; Monodeep Kar; Arvind Singh; Saibal Mukhopadhyay (IEEE Trans. Very Large Scale Integr. Syst., 2019)

25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS. - Amit Agarwal 001; Steven Hsu; Simeon Realov; Mark A. Anders 001; Gregory K. Chen; Monodeep Kar; Raghavan Kumar; Huseyin Sumbul; Phil C. Knag; Himanshu Kaul; Sanu Mathew; Mahesh Kumashikar; et al. (ISSCC, 2020)

25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range. - Mark A. Anders 001; Himanshu Kaul; Seongjong Kim; Gregory K. Chen; Raghavan Kumar; Huseyin Ekin Sumbul; Phil C. Knag; Monodeep Kar; Steven K. Hsu; Amit Agarwal 001; Vikram B. Suresh; Sanu K. Mathew; et al. (ISSCC, 2020)

Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS. - Steven Hsu; Amit Agarwal 001; Simeon Realov; Mark A. Anders 001; Gregory K. Chen; Monodeep Kar; Raghavan Kumar; Huseyin Sumbul; Phil C. Knag; Himanshu Kaul; Vikram B. Suresh; Sanu Mathew; et al. (VLSI Circuits, 2020)

A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications. - Monodeep Kar; Amit Agarwal 001; Steven Hsu; David Moloney; Gregory K. Chen; Raghavan Kumar; Huseyin Sumbul; Phil C. Knag; Mark A. Anders 001; Himanshu Kaul; Jonathan Byrne; Luca Sarti; et al. (VLSI Circuits, 2020)

A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS. - Phil C. Knag; Gregory K. Chen; Huseyin Ekin Sumbul; Raghavan Kumar; Mark A. Anders 001; Himanshu Kaul; Steven K. Hsu; Amit Agarwal 001; Monodeep Kar; Seongjong Kim; Ram K. Krishnamurthy (VLSI Circuits, 2020)

A 4900- $ mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition. - Raghavan Kumar; Vikram B. Suresh; Monodeep Kar; Sudhir Satpathy; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram K. Krishnamurthy; Vivek De; Sanu K. Mathew (IEEE J. Solid State Circuits, 2020)

Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO. - Arvind Singh; Monodeep Kar; Venkata Chaitanya Krishna Chekuri; Sanu K. Mathew; Anand Rajan; Vivek De; Saibal Mukhopadhyay (IEEE J. Solid State Circuits, 2020)

An Inductive Voltage Regulator With Overdrive Tracking Across Input Voltage in Cascoded Power Stage. - Venkata Chaitanya Krishna Chekuri; Monodeep Kar; Arvind Singh; Anto Kavungal Davis; Mohamed Lamine Faycal Bellaredj; Madhavan Swaminathan; Saibal Mukhopadhyay (IEEE Trans. Circuits Syst., 2020)

Methodology of Assessing Information Leakage through Software-Accessible Telemetries. - Chen Liu 013; Monodeep Kar; Xueyang Wang; Nikhil Chawla; Neer Roggel; Bilgiday Yuce; Jason M. Fung (HOST, 2021)

VDPred: Predicting Voltage Droop for Power-Effient 3D Multi-core Processor Design. - He Xiao; Monodeep Kar; Saibal Mukhopadhyay; Sudhakar Yalamanchili (ICCAE, 2021)

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. - Swagath Venkataramani; Vijayalakshmi Srinivasan; Wei Wang 333; Sanchari Sen; Jintao Zhang; Ankur Agrawal; Monodeep Kar; Shubham Jain; Alberto Mannari; Hoang Tran; Yulong Li; Eri Ogawa; et al. (ISCA, 2021)

A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling. - Ankur Agrawal; Sae Kyu Lee; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matt Cohen; Silvia M. Mueller; Jinwook Oh; et al. (ISSCC, 2021)

Securing IoT Devices Using Dynamic Power Management: Machine Learning Approach. - Nikhil Chawla; Arvind Singh; Harshit Kumar; Monodeep Kar; Saibal Mukhopadhyay (IEEE Internet Things J., 2021)

A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS. - Phil C. Knag; Gregory K. Chen; Huseyin Ekin Sumbul; Raghavan Kumar; Steven K. Hsu; Amit Agarwal 001; Monodeep Kar; Seongjong Kim; Mark A. Anders 001; Himanshu Kaul; Ram K. Krishnamurthy (IEEE J. Solid State Circuits, 2021)

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. - Sae Kyu Lee; Ankur Agrawal; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matthew Cohen; Silvia M. Mueller; Jinwook Oh; et al. (IEEE J. Solid State Circuits, 2022)

A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS. - Ankur Agrawal; Monodeep Kar; Kyu-Hyoun Kim; Sergey V. Rylov; Jinwook Jung; Seiji Munetoh; Kohji Hosokawa; Xin Zhang 025; Bahman Hekmatshoartabari; Fabio Carta; Martin Cochet; Robert Casatuta; et al. (VLSI Technology and Circuits, 2023)

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (ISSCC, 2024)

Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (IEEE J. Solid State Circuits, 2025)