The 5ESS switching system: Factory system testing. - John P. Delatore; Monte P. Tull; D. Van Haften (AT&T Tech. J., 1985)

Neural network and fuzzy logic techniques for time series forecasting. - Georgios Lezos; Monte P. Tull (CIFEr, 1999)

Predicting the future with the appropriate embedding dimension and time lag. - Georgios Lezos; Monte P. Tull; Joseph P. Havlicek; Jim Sluss (IJCNN, 1999)

Code Re-ordering for a Class of Reconfigurable Microprocessors. - Brian F. Veale; John K. Antonio; Monte P. Tull (FPL, 2004)

Configuration Steering for a Reconfigurable Superscalar Processor. - Brian F. Veale; John K. Antonio; Monte P. Tull (IPDPS, 2005)

Dynamic configuration steering for a reconfigurable superscalar processor. - Nick A. Mould; Brian F. Veale; Monte P. Tull; John K. Antonio (IPDPS, 2006)

Selection of instruction set extensions for an FPGA embedded processor core. - Brian F. Veale; John K. Antonio; Monte P. Tull; Sean A. Jones (IPDPS, 2006)

Design of steering vectors for dynamically reconfigurable architectures. - Nick A. Mould; Brian F. Veale; John K. Antonio; Monte P. Tull; John R. Junger (IPDPS, 2008)

Prediction aggregation of remote traffic microwave sensors speed and volume data. - John R. Junger; Joseph P. Havlicek; Ronald D. Barnes; Monte P. Tull (ITSC, 2009)

Distributed ITS control and the Oklahoma virtual TMC. - Basel H. Kilani; Ekasit Vorakitolan; Joseph P. Havlicek; Monte P. Tull; Alan R. Stevenson (ITSC, 2009)

Phase-Guided Scheduling on Single-ISA Heterogeneous Multicore Processors. - Lina Sawalha; Sonya R. Wolff; Monte P. Tull; Ronald D. Barnes (DSD, 2011)

Peer-based communication for a distributed, virtual Traffic Management Center. - Basel H. Kilani; Patrick A. Campbell; Joseph P. Havlicek; Monte P. Tull; Alan R. Stevenson; Ronald D. Barnes (ITSC, 2011)

Thread scheduling for heterogeneous multicore processors using phase identification. - Lina Sawalha; Monte P. Tull; Ronald D. Barnes (SIGMETRICS Perform. Evaluation Rev., 2011)