A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and Gm-Regulated Resistive-Feedback Driver. - Haram Ju; Moon-Chul Choi; Gyu-Seob Jeong; Woo-Rham Bae; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOS. - Haram Ju; Moon-Chul Choi; Gyu-Seob Jeong; Deog-Kyoon Jeong (VLSI Circuits, 2018)

A Design of Data Path Based on CMOS Logic for a 72-Gb/s PAM-4 Transmitter in 28-nm CMOS. - Moon-Chul Choi; Haram Ju; Han-Gon Ko; Deog-Kyoon Jeong (ICEIC, 2019)

A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver. - Moon-Chul Choi; Deog-Kyoon Jeong; Sung-Yong Cho; Minkyo Shim; Byungmin Kim; Han-Gon Ko; Haram Ju; Kwanseo Park; Hyojun Kim; Kwandong Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler. - Moon-Chul Choi; Han-Gon Ko; Jonghyun Oh; Hye-Yoon Joo; Kwangho Lee; Deog-Kyoon Jeong (VLSI Circuits, 2020)

A Maximum Eye Tracking Clock-and-Data Recovery Scheme with Golden Section Search(GSS) Algorithm in 28-nm CMOS. - Seungha Roh; Moon-Chul Choi; Deog-Kyoon Jeong (ISOCC, 2021)

A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS. - Byungjun Kang; Gyu-Seob Jeong; Jeongho Hwang; Kwanseo Park; Hyungrok Do; Hyojun Kim; Han-Gon Ko; Moon-Chul Choi; Deog-Kyoon Jeong (IEEE Access, 2021)

A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE. - Moon-Chul Choi; Sanghee Lee 002; Seungha Roh; Kwangho Lee; Jonghyun Oh; Sungwoo Kim 001; Kwandong Kim; Woo-Seok Choi; Jaeha Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 64-Gb/s PAM-4 Receiver With Transition-Weighted Phase Detector. - Seungha Roh; Kwangho Lee; Minkyo Shim; Moon-Chul Choi; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration. - Sung-Yong Cho; Moon-Chul Choi; Jaehyeok Baek; Donggun An; Sanghoon Kim; Daewoong Lee; Seongyeal Yang; Gil-Young Kang; Juseop Park; Kyungho Lee; Hwan-Chul Jung; Gun-hee Cho; et al. (ISSCC, 2024)

30.3 A 24Gb 42.5Gb/s GDDR7 DRAM with Low-Power WCK Distribution, an RC-Optimized Dual-Emphasis TX, and Voltage/Time-Margin-Enhanced Power Reduction. - Sang-Hoon Kim; Jaehyeok Baek; Moon-Chul Choi; Daewoong Lee; Donggun An; Se-Mi Kim; Yeonggeun Song; Minkyo Shim; Sung-Yong Cho; Dongha Lee; Gun-hee Cho; Inwoo Jun; et al. (ISSCC, 2025)

A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration. - Sung-Yong Cho; Moon-Chul Choi; Jaehyeok Baek; Donggun An; Sang-Hoon Kim; Daewoong Lee; Seongyeal Yang; Se-Mi Kim; Gil-Young Kang; Juseop Park; Kyung-Ho Lee; Hwan-Chul Jung; et al. (IEEE J. Solid State Circuits, 2025)