An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme. - Kyu-Hyoun Kim; Uksong Kang; Hoeju Chung; Dukha Park; Woo-Seop Kim; Young-Chan Jang; Moon-Sook Park; Hoon Lee; Jinyoung Kim; Jung Sunwoo; Hwan-Wook Park; Hyun-Kyung Kim; et al. (ISSCC, 2006)

A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter. - Kyu-Hyoun Kim; Young-Soo Sohn; Chan-Kyoung Kim; Moon-Sook Park; Dong-Jin Lee; Woo-Seop Kim; Changhyun Kim (IEEE J. Solid State Circuits, 2006)

An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme. - Kyu-Hyoun Kim; Hoeju Chung; Woo-Seop Kim; Moon-Sook Park; Young-Chan Jang; Jinyoung Kim; Hwan-Wook Park; Uksong Kang; Paul W. Coteus; Joo-Sun Choi; Changhyun Kim (IEEE J. Solid State Circuits, 2007)

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel. - Young-Chan Jang; Hoeju Chung; Youngdon Choi; Hwan-Wook Park; Jaekwan Kim 003; Soouk Lim; Jung Sunwoo; Moon-Sook Park; Hyung-Seuk Kim; Sang-Yun Kim; Yun-Sang Lee; Woo-Seop Kim; et al. (IEEE J. Solid State Circuits, 2009)