Ongoing Evolution of DRAM Scaling via Third Dimension -Vertically Stacked DRAM -. - Jung-Won Han; S. H. Park; Moonyoung Jeong; K. N. Kim; H. J. Kim; J. C. Shin; S. M. Park; S. H. Shin; S. W. Park; K. S. Lee; J. H. Lee; S. H. Kim; et al. (VLSI Technology and Circuits, 2023)

Effect of Back Gate on Word Line Disturb Immunity of a Vertical Channel DRAM Cell Array Transistor. - Moonyoung Jeong; Sangho Lee; Yootak Jun; Kiseok Lee; Seokhan Park; Jeonghoon Oh; Ilgweon Kim; Jemin Park (IRPS, 2024)

Cell to Core-Periphery Overlap (C2O) Based on BCAT for Next Generation DRAM. - Kiseok Lee; Hongjun Lee; Hyungeun Choi; Jeongsu Kim; Kyunghwan Kim; Moonyoung Jeong; Soohyun Bae; Hyebin Kim; Jiyun Lee; Minsoo Kim; Keunnam Kim; Huijung Kim; et al. (VLSI Technology and Circuits, 2024)

A Study on the Origin of Dynamic Charge Loss of Next Generation DRAM Cell Array Transistor. - Moonyoung Jeong; Hyungjun Noh; Sangho Lee; Yootak Jun; Jeonghoon Oh; Jemin Park; Jaihyuk Song (IRPS, 2025)