MIST: monitor generation from informal specifications for firmware verification. - Samuele Germiniani; Moreno Bragaglio; Graziano Pravadelli (VLSI-SOC, 2020)

From Informal Specifications to an ABV Framework for Industrial Firmware Verification. - Samuele Germiniani; Moreno Bragaglio; Graziano Pravadelli (VLSI-SoC (Selected Papers), 2020)

System-level bug explanation through program slicing and instruction clusterization. - Moreno Bragaglio; Nicola Donatelli; Samuele Germiniani; Graziano Pravadelli (VLSI-SoC, 2021)

Exploiting Program Slicing and Instruction Clusterization to Identify the Cause of Faulty Temporal Behaviours at System Level. - Moreno Bragaglio; Samuele Germiniani; Graziano Pravadelli (VLSI-SoC (Selected Papers), 2021)

Assertion-aware approximate computing design exploration on behavioral models. - Alberto Bosio; Moreno Bragaglio; Samuele Germiniani; Samuele Mori; Graziano Pravadelli; Marcello Traiola (LATS, 2022)