SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture. - Kazuaki J. Murakami; Naohiko Irie; Morihiro Kuga; Shinji Tomita (ISCA, 1989)

DSNS (dynamically-hazard-resolved statically-code-scheduled, nonuniform superscalar): yet another superscalar processor architecture. - Morihiro Kuga; Kazuaki J. Murakami; Shinji Tomita (SIGARCH Comput. Archit. News, 1991)

Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations. - Kei Hiraki; Hideharu Amano; Morihiro Kuga; Toshinori Sueyoshi; Tomohiro Kudoh; Hiroshi Nakashima; Hironori Nakajo; Hideo Matsuda; Takashi Matsumoto 002; Shin-ichiro Mori (ISPAN, 1994)

KITE microprocessor and CAE for computer science. - Toshinori Sueyoshi; Morihiro Kuga; Hidetomo Shibamura (Syst. Comput. Jpn., 2002)

EXPRESS-1: a dynamically reconfigurable platform using embedded processor FPGA. - Hidetomo Shibamura; Masayuki Fukuyama; Daisuke Uchida; Seiji Ikeda; Morihiro Kuga; Toshinori Sueyoshi (FPT, 2004)

Memory Sharing Approach for TMR Softcore Processor. - Yoshihiro Ichinomiya; Shiro Tanoue; Tomoyuki Ishida; Motoki Amagasaki; Morihiro Kuga; Toshinori Sueyoshi (ARC, 2009)

A novel states recovery technique for the TMR softcore processor. - Shiro Tanoue; Tomoyuki Ishida; Yoshihiro Ichinomiya; Motoki Amagasaki; Morihiro Kuga; Toshinori Sueyoshi (FPL, 2009)

Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration. - Yoshihiro Ichinomiya; Shiro Tanoue; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FCCM, 2010)

Power-aware FPGA routing fabrics and design tools. - Shoichi Nishida; Jyunya Eto; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (VLSI-SoC, 2010)

Improving the Soft-error Tolerability of a Soft-core Processor on. - Yoshihiro Ichinomiya; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (J. Next Gener. Inf. Technol., 2011)

Parallelization of the channel width search for FPGA routing. - Hiroomi Sawada; Morihiro Kuga; Motoki Amagasaki; Masahiro Iida; Toshinori Sueyoshi (SIGARCH Comput. Archit. News, 2011)

Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams. - Yoshihiro Ichinomiya; Sadaki Usagawa; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FCCM, 2012)

Fault detection and avoidance of FPGA in various granularities. - Kazuki Inoue; Yuki Nishitani; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPL, 2012)

Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration. - Yoshihiro Ichinomiya; Kohei Takano; Motoki Amagasaki; Morihiro Kuga; Masahiro Iida; Toshinori Sueyoshi (FPT, 2012)

Fault Recovery Technique for TMR Softcore Processor System Using Partial Reconfiguration. - Makoto Fujino; Hiroki Tanaka; Yoshihiro Ichinomiya; Motoki Amagasaki; Morihiro Kuga; Masahiro Iida; Toshinori Sueyoshi (ICA3PP (1), 2012)

A Bitstream Relocation Technique to Improve Flexibility of Partial Reconfiguration. - Yoshihiro Ichinomiya; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (ICA3PP (1), 2012)

A novel physical defects recovery technique for FPGA-IP cores. - Yuki Nishitani; Kazuki Inoue; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (ReConFig, 2012)

Evaluation of fault tolerant technique based on homogeneous FPGA architecture. - Yuki Nishitani; Kazuki Inoue; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (VLSI-SoC, 2012)

Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration. - Yoshihiro Ichinomiya; Tsuyoshi Kimura; Motoki Amagasaki; Morihiro Kuga; Masahiro Iida; Toshinori Sueyoshi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

A novel FPGA design framework with VLSI post-routing performance analysis (abstract only). - Qian Zhao 001; Kazuki Inoue; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPGA, 2013)

Defect-robust FPGA architectures for intellectual property cores in system LSI. - Motoki Amagasaki; Kazuki Inoue; Qian Zhao 001; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPL, 2013)

An automatic FPGA design and implementation framework. - Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPL, 2013)

An FPGA design and implementation framework combined with commercial VLSI CADs. - Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (ReCoSoC, 2013)

Three-dimensional stacking FPGA architecture using face-to-face integration. - Tetsuro Hamada; Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (VLSI-SoC, 2013)

FPGA Design Framework Combined with Commercial VLSI CAD. - Qian Zhao 001; Kazuki Inoue; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2013)

A reconfigurable Java accelerator with software compatibility for embedded systems. - Yuki Ogawa; Masahiro Iida; Motoki Amagasaki; Morihiro Kuga; Toshinori Sueyoshi (SIGARCH Comput. Archit. News, 2013)

A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory. - Qian Zhao 001; Kyosei Yanagida; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPL, 2014)

Zyndroid: An Android platform for software/hardware coprocessing. - Susumu Mashimo; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPT, 2014)

Blokus Duo engine on a Zynq. - Susumu Mashimo; Kansuke Fukuda; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPT, 2014)

Simple wafer stacking 3D-FPGA architecture. - Motoki Amagasaki; Qian Zhao 001; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (ICICDT, 2015)

Architecture exploration of 3D FPGA to minimize internal layer connection. - Motoki Amagasaki; Yuto Takeuchi; Qian Zhao 001; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (VLSI-SoC, 2015)

Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC. - Motoki Amagasaki; Qian Zhao 001; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2015)

A 3D FPGA Architecture to Realize Simple Die Stacking. - Motoki Amagasaki; Qian Zhao 001; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (IPSJ Trans. Syst. LSI Des. Methodol., 2015)

hCODE: An open-source platform for FPGA accelerators. - Qian Zhao 001; Takuya Nakamichi; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPT, 2016)

A Study of Heterogeneous Computing Design Method based on Virtualization Technology. - Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (SIGARCH Comput. Archit. News, 2016)

hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds. - Qian Zhao 001; Hendarmawan; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPT, 2017)

FPGA based ASIC Emulator with High Speed Optical Serial Links. - Motoki Amagasaki; Futoshi Murase; Morihiro Kuga; Masahiro Iida; Toshinori Sueyoshi (HEART, 2017)

High-level Synthesis based on Parallel Design Patterns using a Functional Language. - Morihiro Kuga; Kansuke Fukuda; Motoki Amagasaki; Masahiro Iida; Toshinori Sueyoshi (HEART, 2017)

Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core. - Motoki Amagasaki; Yuki Nishitani; Kazuki Inoue; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2017)

Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost. - Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (IPSJ Trans. Syst. LSI Des. Methodol., 2017)

Enabling FPGA-as-a-Service in the Cloud with hCODE Platform. - Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2018)

Automation of Domain-specific FPGA-IP Generation and Test. - Yuya Nakazato; Motoki Amagasaki; Qian Zhao 001; Masahiro Iida; Morihiro Kuga (HEART, 2021)

FPL Demo: An FPGA-IP Prototype Chip for MEC devices. - Morihiro Kuga; Masahiro Iida; Hideharu Amano (FPL, 2022)

An eFPGA Generation Suite with Customizable Architecture and IDE. - Morihiro Kuga; Qian Zhao 001; Yuya Nakazato; Motoki Amagasaki; Masahiro Iida (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)

SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks. - Takuya Kojima; Yosuke Yanai; Hayate Okuhara; Hideharu Amano; Morihiro Kuga; Masahiro Iida (COOL CHIPS, 2024)

Applying Run-Length Compression to the Configuration Data of SLM Fine-Grained Reconfigurable Logic. - Souhei Takagi; Takuya Kojima; Hideharu Amano; Morihiro Kuga; Masahiro Iida (IEICE Trans. Inf. Syst., 2024)