Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed on 576 digital neurons. - Moritoshi Yasunaga; Noboru Masuda; Masayoshi Yagyu; Mitsuo Asai; Minoru Yamada; Akira Masaki (IJCNN, 1990)

Wafer Scale Integration for Massively Parallel Memory-Based Reasoning. - Hiroaki Kitano; Moritoshi Yasunaga (AAAI, 1992)

A self-learning digital neural network using wafer-scale LSI. - Moritoshi Yasunaga; Noboru Masuda; Masayoshi Yagyu; Mitsuo Asai; Katsunari Shibata; Mitsuo Ooyama; Minoru Yamada; Takahiro Sakaguchi; Masashi Hashimoto (IEEE J. Solid State Circuits, 1993)

Ising model calculation using PDM neural network hardware: Boltzmann statistical mechanics embedded in the hardware. - Moritoshi Yasunaga; Yuzo Hirai (ICNN, 1997)

Dynamic Optical Topography and the Real-Time PDP Chip: An Analytical and Synthetical Approach to Higher-Order Brain Functions. - Hirokazu Koizumi; T. Ochiai; T. Okahashi; Y. Yamashita; A. Maki; T. Yamamoto; Y. Inagami; H. Yoshizawa; Masaya Iwata; Takashi Omori; Moritoshi Yasunaga (ICONIP, 1998)

Performance of a bus-based parallel computer with integer-representation processors applied to artificial neural network and parallel AI domains. - Moritoshi Yasunaga; Akio Yamada; T. Okahashi (KES (3), 1998)

Fault-tolerant self-organizing map implemented by wafer-scale integration. - Moritoshi Yasunaga; I. Hachiya; K. Moki; Jung Hwan Kim (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Sonar spectrum recognition chip designed by evolutionary algorithm. - Moritoshi Yasunaga; Taro Nakamura; Ikuo Yoshihara (IJCNN, 1999)

Parallel self-organization map using multiple stimuli. - Moritoshi Yasunaga; Kenichi Tominaga; Jung Hwan Kim (IJCNN, 1999)

Parallel back-propagation using genetic algorithm: real-time BP learning on the massively parallel computer CP-PACS. - Moritoshi Yasunaga; Eiji Yoshida; Ikuo Yoshihara (IJCNN, 1999)

A multi-modal neural network using Chebyschev polynomials and its application. - Ikuo Yoshihara; Tomoyuki Nakagawa; Moritoshi Yasunaga; Kenichi Abe (IJCNN, 1999)

GA-based kernel optimization for pattern recognition: theory for EHW application. - Moritoshi Yasunaga; Taro Nakamura; Ikuo Yoshihara; Jung H. Kim (CEC, 2000)

GP-based modeling method for time series prediction with parameter optimization and node alternation. - Ikuo Yoshihara; Tomoo Aoyama; Moritoshi Yasunaga (CEC, 2000)

A High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI. - Moritoshi Yasunaga; Ikuo Yoshihara; Jung Hwan Kim (DFT, 2000)

Kernel-Based Pattern Recognition Hardware: Its Design Methodology Using Evolved Truth Tables. - Moritoshi Yasunaga; Taro Nakamura; Jung Hwan Kim; Ikuo Yoshihara (Evolvable Hardware, 2000)

The application of genetic algorithms to the design of reconfigurable reasoning VLSI chips. - Moritoshi Yasunaga; Jung Hwan Kim; Ikuo Yoshihara (FPGA, 2000)

Kernel Optimization in Pattern Recognition Using a Genetic Algorithm. - Moritoshi Yasunaga; Taro Nakamura; Ikuo Yoshihara; Jung Hwan Kim (GECCO, 2000)

A Fast Model-Building Method for Time Series Using Genetic Programming. - Ikuo Yoshihara; Tomoo Aoyama; Moritoshi Yasunaga (GECCO, 2000)

Genetic Algorithm-Based Methodology for Pattern Recognition Hardware. - Moritoshi Yasunaga; Taro Nakamura; Ikuo Yoshihara; Jung Hwan Kim (ICES, 2000)

Evolvable reasoning hardware: its application to the genome informatics. - Moritoshi Yasunaga; Takahiro Tsuzuku; Kentaro Ushiyama; Ikuo Yoshihara; Jung H. Kim (CEC, 2001)

Evolvable Reasoning Hardware: Its Prototyping and Performance Evaluation. - Moritoshi Yasunaga; Jung Hwan Kim; Ikuo Yoshihara (Genet. Program. Evolvable Mach., 2001)

Robust noncoherent PN-code acquisition for CDMA communication systems. - Jung Hwan Kim; Shanuj V. Sarin; Moritoshi Yasunaga; Hyunseo Oh (IEEE Trans. Veh. Technol., 2001)

A parallel hybrid genetic algorithm for multiple protein sequence alignment. - Hung Dinh Nguyen 003; Ikuo Yoshihara; Kunihito Yamamori; Moritoshi Yasunaga (IEEE Congress on Evolutionary Computation, 2002)

An evolutionary kernel-based reasoning system using reconfigurable VLSIs: its hardware prototyping and application to the splicing boundary problem. - Moritoshi Yasunaga; Kentaro Ushiyama; Noriyuki Aibe; Hidetoshi Fujiwara; Ikuo Yoshiyara; Jung H. Kim (IEEE Congress on Evolutionary Computation, 2002)

Prediction of protein secondary Structure by Multi-Modal Neural Networks. - Hanxi Zhu; Ikuo Yoshihara; Kunihito Yamamori; Moritoshi Yasunaga (SEAL, 2002)

Improved GA-based method for multiple protein sequence alignment. - Hung Dinh Nguyen 003; Kunihito Yamamori; Ikuo Yoshihara; Moritoshi Yasunaga (IEEE Congress on Evolutionary Computation, 2003)

The design of segmental-transmission-line for high-speed digital signals using genetic algorithms. - Moritoshi Yasunaga; Ikuo Yoshihara; Jung Hwan Kim (IEEE Congress on Evolutionary Computation, 2003)

Reconfigurable parallel comparation architecture and its application to IP packet filters. - Noriyuki Aibe; Moritoshi Yasunaga (FPT, 2003)

Reconfigurable architecture for probabilistic neural network system. - Ryosuke Mizuno; Noriyuki Aibe; Moritoshi Yasunaga; Ikuo Yoshihara (FPT, 2003)

Gene Finding Using Evolvable Reasoning Hardware. - Moritoshi Yasunaga; Ikuo Yoshihara; Jung Hwan Kim (ICES, 2003)

A computational approach to detect regulatory elements in Dictyostelium discoideum. - Daekwan Seo; Moritoshi Yasunaga; Jung Hwan Kim (IEEE Congress on Evolutionary Computation, 2004)

Reconfigurable I/O interface for mobile equipments. - Noriyuki Aibe; Moritoshi Yasunaga (FPT, 2004)

Performance evaluation system for probabilistic neural network hardware. - Noriyuki Aibe; Ryosuke Mizuno; Masanori Nakamura; Moritoshi Yasunaga; Ikuo Yoshihara (Artif. Life Robotics, 2004)

A multimodal neural network with single-state predictions for protein secondary structure. - Hanxi Zhu; Ikuo Yoshihara; Kunihito Yamamori; Moritoshi Yasunaga (Artif. Life Robotics, 2004)

Multi-Modal Neural Networks for Symbolic Sequence Pattern Classification. - Hanxi Zhu; Ikuo Yoshihara; Kunihito Yamamori; Moritoshi Yasunaga (IEICE Trans. Inf. Syst., 2004)

Variable length segmental-transmission-line and its parameter optimization based on GA. - Naoki Koizumi; Ikuo Yoshihara; Kunihito Yamamori; Moritoshi Yasunaga (Congress on Evolutionary Computation, 2005)

Finding transcriptional regulatory elements in Dictyostelium gene expression. - Daekwan Seo; Moritoshi Yasunaga; Insook Kim; Byungwoon Ham; Jung Hwan Kim (Congress on Evolutionary Computation, 2005)

On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition. - Kyrre Glette; Jim Tørresen; Moritoshi Yasunaga; Yoshiki Yamaguchi (AHS, 2006)

Enhancement of the Variable-Length-Transmission-Line design method for multi-point optimization. - Naoki Koizumi; Ikuo Yoshihara; Kunihito Yamamori; Moritoshi Yasunaga (IEEE Congress on Evolutionary Computation, 2006)

Realization of the sound space environment for the radiation-tolerant space craft. - Hiroyuki Kawai; Yoshiki Yamaguchi; Moritoshi Yasunaga (ReConFig, 2006)

Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA. - Kyrre Glette; Jim Tørresen; Moritoshi Yasunaga (AHS, 2007)

An Online EHW Pattern Recognition System Applied to Face Image Recognition. - Kyrre Glette; Jim Tørresen; Moritoshi Yasunaga (EvoWorkshops, 2007)

An Online EHW Pattern Recognition System Applied to Sonar Spectrum Classification. - Kyrre Glette; Jim Tørresen; Moritoshi Yasunaga (ICES, 2007)

Bio-Inspired Functional Asymmetry Camera System. - Yoshiki Yamaguchi; Noriyuki Aibe; Moritoshi Yasunaga; Yorihisa Yamamoto; Takaaki Awano; Ikuo Yoshihara (ICONIP (2), 2007)

A Lattice Gas Cellular Automata Simulator on the Cell Broadband Engine. - Yusuke Arai; Ryo Sawai; Yoshiki Yamaguchi; Tsutomu Maruyama; Moritoshi Yasunaga (PARCO, 2007)

A bio-inspired tracking camera system. - Yoshiki Yamaguchi; Moritoshi Yasunaga; Kazuya Hayashi; Noriyuki Aibe; Yorihisa Yamamoto; Ikuo Yoshihara (Artif. Life Robotics, 2007)

A New Three-Level Tree Data Structure for Representing TSP Tours in the Lin-Kernighan Heuristic. - Hung Dinh Nguyen 003; Ikuo Yoshihara; Kunihito Yamamori; Moritoshi Yasunaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Implementation of an Effective Hybrid GA for Large-Scale Traveling Salesman Problems. - Hung Dinh Nguyen 003; Ikuo Yoshihara; Kunihito Yamamori; Moritoshi Yasunaga (IEEE Trans. Syst. Man Cybern. Part B, 2007)

Mesoscopic-level Simulation of Dynamics and Interactions of Biological Molecules Using Monte Carlo Simulation. - Yoshiki Yamaguchi; Tsutomu Maruyama; Ryuzo Azuma; Moritoshi Yasunaga; Akihiko Konagaya (J. VLSI Signal Process., 2007)

An adaptive pattern recognition hardware with on-chip shift register-based partial reconfiguration. - Hiroyuki Kawai; Yoshiki Yamaguchi; Moritoshi Yasunaga; Kyrre Glette; Jim Tørresen (FPT, 2008)

The Segmental-Transmission-Line: Its Design and Prototype Evaluation. - Moritoshi Yasunaga; Yoshiki Yamaguchi; Hiroshi Nakayama; Ikuo Yoshihara; Naoki Koizumi; Jung Hwan Kim (ICES, 2008)

Variable-length segmental transmission line and its design guidelines. - Naoki Koizumi; Kazuya Hayashi; Moritoshi Yasunaga; Kunihito Yamamori; Ikuo Yoshihara (Artif. Life Robotics, 2008)

Real-world applications on the reconfigurable-VLSI-based double-lens tracking-camera. - Moritoshi Yasunaga; Noriyuki Aibe; Yoshiki Yamaguchi; Yorihisa Yamamoto; Takaaki Awano; Ikuo Yoshihara (Artif. Life Robotics, 2008)

A reconfigurable VLSI-based double-lens tracking camera. - Moritoshi Yasunaga; Noriyuki Aibe; Yoshiki Yamaguchi; Yorihisa Yamamoto; Takaaki Awano; Ikuo Yoshihara (Artif. Life Robotics, 2008)

A visual-inspection system using a self-organizing map. - Keiko Ikeda; Moritoshi Yasunaga; Yoshiki Yamaguchi; Yorihisa Yamamoto; Ikuo Yoshihara (Artif. Life Robotics, 2009)

A proposal for Zoning Crossover of Hybrid Genetic Algorithms for large-scale traveling salesman problems. - Masafumi Kuroda; Kunihito Yamamori; Masaharu Munetomo; Moritoshi Yasunaga; Ikuo Yoshihara (IEEE Congress on Evolutionary Computation, 2010)

Signal-integrity improvement method and its robustness evaluation for VLSI and VLSI-packaging. - Masami Ishiguro; Hiroshi Nakayama; Yuki Shimauchi; Noriyuki Aibe; Ikuo Yoshihara; Moritoshi Yasunaga (Artif. Life Robotics, 2010)

Development of a novel crossover of hybrid genetic algorithms for large-scale traveling salesman problems. - Masafumi Kuroda; Kunihito Yamamori; Masaharu Munetomo; Moritoshi Yasunaga; Ikuo Yoshihara (Artif. Life Robotics, 2010)

Digital-signal-waveform improvement on VLSI packaging including inductances. - Hiroki Shimada; Shohei Akita; Masami Ishiguro; Noriyuki Aibe; Ikuo Yoshihara; Moritoshi Yasunaga (Artif. Life Robotics, 2011)

Segmental transmission line: Its practical application the optimized PCB trace design using a genetic algorithm. - Moritoshi Yasunaga; Hiroki Shimada; Katsuyuki Seki; Ikuo Yoshihara (ICES, 2014)

High-Speed Calculation of Convex Hull in 2D Images Using FPGA. - Kenji Kanazawa; Kahori Kemmotsu; Yamato Mori; Noriyuki Aibe; Moritoshi Yasunaga (PARCO, 2015)

Simultaneous Improvement to Signal Integrity and Electromagnetic Interference in High-Speed Transmission Lines. - Moritoshi Yasunaga; Yusuke Kuribara; Hirofumi Inoue; Ikuo Yoshihara (SSCI, 2015)

Foreword. - Moritoshi Yasunaga (IEICE Trans. Inf. Syst., 2015)

A passive equalizer and its design methodology for global interconnects in VLSIs. - Moritoshi Yasunaga; Naoki Yokoshima; Ikuo Yoshihara (VLSI-SoC, 2016)

An evolutionary design methodology of printed circuit boards for high-speed VLSIs. - Moritoshi Yasunaga; Ikuo Yoshihara (Artif. Life Robotics, 2016)

An FPGA Solver for Partial MaxSAT Problems Based on Stochastic Local Search. - Shohei Sassa; Kenji Kanazawa; Shaowei Cai 001; Moritoshi Yasunaga (SIGARCH Comput. Archit. News, 2016)

Evolutionary design of high signal integrity interconnection based on eye-diagram. - Tetsuya Odaira; Naoki Yokoshima; Ikuo Yoshihara; Moritoshi Yasunaga (Artif. Life Robotics, 2018)

FPGA-Based Object Detection for Autonomous Driving System. - Kenichi Harada; Kenji Kanazawa; Moritoshi Yasunaga (FPT, 2019)

FPGA Implementation of Minimum Spanning Tree Calculation Towards Application for Capacitated Vehicle Routing Problems. - Jiheng Wang; Kenji Kanazawa; Moritoshi Yasunaga (ICCE, 2024)

A FPGA-based Learning Accelerator for Self-Organizing Map and Its Application to Trend-Visualization. - Yusuke Yamagiwa; Kenji Kanazawa; Moritoshi Yasunaga (ICCE, 2024)

A highly scalable Self-organizing Map accelerator on FPGA and its performance evaluation. - Yusuke Yamagiwa; Yuki Kawahara; Kenji Kanazawa; Moritoshi Yasunaga (Artif. Life Robotics, 2024)