Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs. - Anthony Agnesina; Moritz Brunion; Jinwoo Kim; Alberto García Ortiz; Dragomir Milojevic; Francky Catthoor; Manu Perumkunnil; Sung Kyu Lim (ISLPED, 2021)

MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration. - Matheus A. Cavalcante; Anthony Agnesina; Samuel Riedel; Moritz Brunion; Alberto García-Ortiz; Dragomir Milojevic; Francky Catthoor; Sung Kyu Lim; Luca Benini (DATE, 2022)

Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs. - Anthony Agnesina; Moritz Brunion; Alberto García Ortiz; Francky Catthoor; Dragomir Milojevic; Manu Komalan; Matheus A. Cavalcante; Samuel Riedel; Luca Benini; Sung Kyu Lim (ISLPED, 2022)

Thermal Performance Analysis of Mempool RISC-V Multicore SoC. - Sankatali Venkateswarlu; Subrat Mishra; Herman Oprins; Bjorn Vermeersch; Moritz Brunion; Jun-Han Han; Mircea R. Stan; Pieter Weckx; Francky Catthoor (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs. - Mohamed Naeim; Hanqi Yang; Pinhong Chen; Rong Bao; Antoine Dekeyser; Giuliano Sisto; Moritz Brunion; Rongmei Chen; Geert Van der Plas; Eric Beyne; Dragomir Milojevic (3DIC, 2023)

Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs). - Subrat Mishra; Sankatali Venkateswarlu; Bjorn Vermeersch; Moritz Brunion; Melina Lofrano; Dawit Burusie Abdi; Herman Oprins; Dwaipayan Biswas; Odysseas Zografos; Gaspard Hiblot; Geert Van der Plas; Pieter Weckx; et al. (IRPS, 2023)

On Legalization of Die Bonding Bumps and Pads for 3D ICs. - Sai Pentapati; Anthony Agnesina; Moritz Brunion; Yen-Hsiang Huang; Sung Kyu Lim (ISPD, 2023)

Impact of 3-D Integration on Thermal Performance of RISC-V MemPool Multicore SOC. - Sankatali Venkateswarlu; Subrat Mishra; Herman Oprins; Bjorn Vermeersch; Moritz Brunion; Jun-Han Han; Mircea R. Stan; Dwaipayan Biswas; Pieter Weckx; Francky Catthoor (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Thermal Analysis of High-Performance Server SoCs from FinFET to Nanosheet Technologies. - Nitish Kumar; Sankatali Venkateswarlu; Yukai Chen; Moritz Brunion; Subrat Mishra; Ankur Gupta; Pushpapraj Singh; Francky Catthoor; James Myers; Julien Ryckaert; Dwaipayan Biswas (IRPS, 2024)

Thermal Performance Evaluation of Multi-Core SOCs Using Power-Thermal Co-Simulation. - Subrat Mishra; Bjorn Vermeersch; Sankatali Venkateswarlu; Halil Kukner; A. Sharma; G. Mirabeli; Fabian M. Bufler; Moritz Brunion; Dawit Burusie Abdi; Herman Oprins; Dwaipayan Biswas; Odysseas Zografos; et al. (IRPS, 2024)

3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs. - Sudipta Das; Samuel Riedel; Marco Bertuletti; Luca Benini; Moritz Brunion; Julien Ryckaert; James Myers; Dwaipayan Biswas; Dragomir Milojevic (ISCAS, 2024)

Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5). - S. Mishra; Bjorn Vermeersch; Sankatali Venkateswarlu; Halil Kukner; Gioele Mirabelli; Fabian M. Bufler; Moritz Brunion; Dawit Burusie Abdi; Herman Oprins; Dwaipayan Biswas; Odysseas Zografos; Francky Catthoor; et al. (VLSI Technology and Circuits, 2024)

Backside Power Delivery in High Density and High Performance Context: IR-Drop and Block-Level Power-Performance-Area Benefits. - Yun Zhou; S. C. Song; Halil Kükner; Giuliano Sisto; Sheng Yang; Anita Farokhnejad; Mohamed Naeim; Moritz Brunion; Ji-Yung Lin; Odysseas Zografos; Pieter Weckx; Shashank Ekbote; et al. (VLSI Technology and Circuits, 2024)

Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs. - Nesara Eranna Bethur; Anthony Agnesina; Moritz Brunion; Alberto García Ortiz; Francky Catthoor; Dragomir Milojevic; Manu Komalan; Matheus A. Cavalcante; Samuel Riedel; Luca Benini; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

On Legalization of Die Bonding Bumps and Pads for 3-D ICs. - Yen-Hsiang Huang; Sai Pentapati; Anthony Agnesina; Moritz Brunion; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC. - Sudipta Das; Samuel Riedel; Mohamed Naeim; Moritz Brunion; Marco Bertuletti; Luca Benini; Julien Ryckaert; James Myers; Dwaipayan Biswas; Dragomir Milojevic (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes. - Lorenzo Ruotolo; Lara Orlandic; Pengbo Yu; Moritz Brunion; Daniele Jahier Pagliari; Dwaipayan Biswas; Giovanni Ansaloni; David Atienza; Julien Ryckaert; Francky Catthoor; Yukai Chen (CoRR, 2025)