Architectural Synthesis with Control Data Flow Extraction toward an Asynchronous CAD Tool. - Morteza Damavandpeyma; Siamak Mohammadi (DSD, 2008)

Delay testing of PD-SOI circuits. - Morteza Damavandpeyma; Rasoul Yousefi; Behjat Forouzandeh (IEICE Electron. Express, 2008)

Thermal-aware scratchpad memory design and allocation. - Morteza Damavandpeyma; Sander Stuijk; Twan Basten; Marc Geilen; Henk Corporaal (ICCD, 2010)

Hybrid Code-Data Prefetch-Aware Multiprocessor Task Graph Scheduling. - Morteza Damavandpeyma; Sander Stuijk; Twan Basten; Marc Geilen; Henk Corporaal (DSD, 2011)

Modeling static-order schedules in synchronous dataflow graphs. - Morteza Damavandpeyma; Sander Stuijk; Twan Basten; Marc Geilen; Henk Corporaal (DATE, 2012)

Parametric throughput analysis of scenario-aware dataflow graphs. - Morteza Damavandpeyma; Sander Stuijk; Marc Geilen; Twan Basten; Henk Corporaal (ICCD, 2012)

Throughput-constrained DVFS for scenario-aware dataflow graphs. - Morteza Damavandpeyma; Sander Stuijk; Twan Basten; Marc Geilen; Henk Corporaal (IEEE Real-Time and Embedded Technology and Applications Symposium, 2013)

Schedule-Extended Synchronous Dataflow Graphs. - Morteza Damavandpeyma; Sander Stuijk; Twan Basten; Marc Geilen; Henk Corporaal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)