Structural relations between brain-behavioral systems, social anxiety, depression and internet addiction: With regard to revised Reinforcement Sensitivity Theory (r-RST). - Morteza Fayazi; Jafar Hasani (Comput. Hum. Behav., 2017)

A Simplified Approach to Two-Port Analysis in Feedback. - Morteza Fayazi; Ali Fotowat; Zahra Kavehvash (CoRR, 2019)

An Open-source Framework for Autonomous SoC Design with Analog Block Generation. - Tutu Ajayi; Sumanth Kamineni; Yaswanth K. Cherivirala; Morteza Fayazi; Kyumin Kwon; Mehdi Saligane; Shourya Gupta; Chien-Hen Chen; Dennis Sylvester; David T. Blaauw; Ronald G. Dreslinski; Benton H. Calhoun; et al. (VLSI-SOC, 2020)

Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation. - Tutu Ajayi; Sumanth Kamineni; Morteza Fayazi; Yaswanth K. Cherivirala; Kyumin Kwon; Shourya Gupta; Wenbo Duan; Jeongsup Lee; Chien-Hen Chen; Mehdi Saligane; Dennis Sylvester; David T. Blaauw; et al. (VLSI-SoC (Selected Papers), 2020)

Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm. - Sung Kim; Morteza Fayazi; Alhad Daftardar; Kuan-Yu Chen 001; Jielun Tan; Subhankar Pal; Tutu Ajayi; Yan Xiong 002; Trevor N. Mudge; Chaitali Chakrabarti; David T. Blaauw; Ronald G. Dreslinski; et al. (VLSI Circuits, 2021)

Applications of Artificial Intelligence on the Modeling and Optimization for Analog and Mixed-Signal Circuits: A Review. - Morteza Fayazi; Zachary Colter; Ehsan Afshari; Ronald G. Dreslinski (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET. - Kuan-Yu Chen 001; Chi-Sheng Yang; Yu-Hsiu Sun; Chien-Wei Tseng; Morteza Fayazi; Xin He; Siying Feng; Yufan Yue; Trevor N. Mudge; Ronald G. Dreslinski; Hun-Seok Kim; David T. Blaauw (VLSI Technology and Circuits, 2022)

Tablext: A combined neural network and heuristic based table extractor. - Zach Colter; Morteza Fayazi; Zineb Benameur-El Youbi; Serafina Kamp; Shuyan Yu; Ronald G. Dreslinski (Array, 2022)

Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory. - Sung Kim; Morteza Fayazi; Alhad Daftardar; Kuan-Yu Chen 001; Jielun Tan; Subhankar Pal; Tutu Ajayi; Yan Xiong 002; Trevor N. Mudge; Chaitali Chakrabarti; David T. Blaauw; Ronald G. Dreslinski; et al. (IEEE J. Solid State Circuits, 2022)

FASCINET: A Fully Automated Single-Board Computer Generator Using Neural Networks. - Morteza Fayazi; Zachary Colter; Zineb Benameur-El Youbi; Javad Bagherzadeh; Tutu Ajayi; Ronald G. Dreslinski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Compact CMOS 363 GHz Autodyne FMCW Radar with 57 GHz Bandwidth for Dental Imaging. - Morteza Tavakoli Taba; S. M. Hossein Naghavi; Morteza Fayazi; Ali Sadeghi; Andreia Cathelin; Ehsan Afshari (CICC, 2023)

FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method. - Morteza Fayazi; Morteza Tavakoli Taba; Amirata Tabatabavakili; Ehsan Afshari; Ronald G. Dreslinski (ICCAD, 2023)

Open Information Extraction: A Review of Baseline Techniques, Approaches, and Applications. - Serafina Kamp; Morteza Fayazi; Zineb Benameur-El Youbi; Shuyan Yu; Ronald G. Dreslinski (CoRR, 2023)

AnGeL: Fully-Automated Analog Circuit Generator Using a Neural Network Assisted Semi-Supervised Learning Approach. - Morteza Fayazi; Morteza Tavakoli Taba; Ehsan Afshari; Ronald G. Dreslinski (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication. - Kuan-Yu Chen 001; Thomas Mason Nelson; Alireza Khadem; Morteza Fayazi; Sanjay Sri Vallabh Singapuram; Ronald G. Dreslinski; Nishil Talati; Hun-Seok Kim; David T. Blaauw (ACM Trans. Reconfigurable Technol. Syst., 2024)

DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFET. - Kuan-Yu Chen 001; Chi-Sheng Yang; Yu-Hsiu Sun; Chien-Wei Tseng; Morteza Fayazi; Xin He; Siying Feng; Yufan Yue; Trevor N. Mudge; Ronald G. Dreslinski; Hun-Seok Kim; David T. Blaauw (IEEE J. Solid State Circuits, 2025)

MuaLLM: A Multimodal Large Language Model Agent for Circuit Design Assistance with Hybrid Contextual Retrieval-Augmented Generation. - Pravallika Abbineni; Saoud Aldowaish; Colin Liechty; Soroosh Noorzad; Ali Ghazizadeh; Morteza Fayazi (CoRR, 2025)