A neural network approach to the placement problem. - Morteza Saheb Zamani; Graham R. Hellestrand (ASP-DAC, 1995)

Placement with self-organising neural networks. - Morteza Saheb Zamani; Graham R. Hellestrand (ICNN, 1995)

A Stepwise Refinement Algorithm for Integrated Floorplanning, Placement and Routing of Hierarchical Designs. - Morteza Saheb Zamani; Graham R. Hellestrand (ISCAS, 1995)

A New Neural Network Approach to the Floorplanning of Hierarchical VLSI Designs. - Morteza Saheb Zamani; Graham R. Hellestrand (IWANN, 1995)

An efficient method for placement of VLSI designs with Kohonen map. - Morteza Saheb Zamani; Farhad Mehdipour (IJCNN, 1999)

Rectilinear floorplanning of FPGAs using Kohonen map. - Morteza Saheb Zamani; Masoud Soleimani (IJCNN, 2003)

A novel reconfigurable hardware architecture for IP address lookup. - Hamid Fadishei; Morteza Saheb Zamani; Masoud Sabaei (ANCS, 2005)

Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems. - Farhad Mehdipour; Morteza Saheb Zamani; Mehdi Sedighi (DSD, 2005)

Cellular Learning Automata based Evolutionary Computing (CLA-EC) for Intrinsic Hardware Evolution. - Arash Hariri; Reza Rastegar; Keivan Navi; Morteza Saheb Zamani; Mohammad Reza Meybodi (Evolvable Hardware, 2005)

Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA. - Arash Hariri; Reza Rastegar; Morteza Saheb Zamani; Mohammad Reza Meybodi (FCCM, 2005)

A Reconfigurable Architecture for Implementing Multiple Cipher Algorithms. - Ali Valizadeh; Morteza Saheb Zamani; Babak Sadeghian; Farhad Mehdipour (FPT, 2005)

An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. - Farhad Mehdipour; Hamid Noori; Morteza Saheb Zamani; Kazuaki J. Murakami; Mehdi Sedighi; Koji Inoue (Asia-Pacific Computer Systems Architecture Conference, 2006)

GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs. - Farhad Mehdipour; Morteza Saheb Zamani; Mehdi Sedighi; Kazuaki J. Murakami; Hamid Noori (ERSA, 2006)

Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. - Farhad Mehdipour; Hamid Noori; Morteza Saheb Zamani; Kazuaki J. Murakami; Koji Inoue; Mehdi Sedighi (EUC, 2006)

A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. - Hamid Noori; Farhad Mehdipour; Kazuaki J. Murakami; Koji Inoue; Morteza Saheb Zamani (FPL, 2006)

Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework. - Farhad Mehdipour; Morteza Saheb Zamani; Hamid Reza Ahmadifar; Mehdi Sedighi; Kazuaki J. Murakami (IPDPS, 2006)

Prediction and reduction of routing congestion. - Mehdi Saeedi; Morteza Saheb Zamani; Ali Jahanian 001 (ISPD, 2006)

Multi-Level Buffer Block Planning and Buffer Insertion for Large Design Circuits. - Ali Jahanian 001; Morteza Saheb Zamani (ISVLSI, 2006)

An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems. - Farhad Mehdipour; Morteza Saheb Zamani; Mehdi Sedighi (Microprocess. Microsystems, 2006)

Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis. - Mehdi Saeedi; Morteza Saheb Zamani; Mehdi Sedighi (DSD, 2007)

Improved timing closure by early buffer planning in floor-placement design flow. - Ali Jahanian 001; Morteza Saheb Zamani (ACM Great Lakes Symposium on VLSI, 2007)

An efficient net ordering algorithm for buffer insertion. - Hamid Reza Kheirabadi; Morteza Saheb Zamani (ACM Great Lakes Symposium on VLSI, 2007)

A novel synthesis algorithm for reversible circuits. - Mehdi Saeedi; Mehdi Sedighi; Morteza Saheb Zamani (ICCAD, 2007)

Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator. - Hamid Noori; Farhad Mehdipour; Morteza Saheb Zamani; Koji Inoue; Kazuaki J. Murakami (ICESS, 2007)

An Efficient Analytical Approach to Path-Based Buffer Insertion. - Hamid Reza Kheirabadi; Morteza Saheb Zamani; Mehdi Saeedi (ISVLSI, 2007)

On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement. - Mehdi Saeedi; Morteza Saheb Zamani; Mehdi Sedighi (ISVLSI, 2007)

An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor. - Arash Mehdizadeh; Behnam Ghavami; Morteza Saheb Zamani; Hossein Pedram; Farhad Mehdipour (VLSI-SoC, 2007)

Metro-on-chip: an efficient physical design technique for congestion reduction. - Ali Jahanian 001; Morteza Saheb Zamani (IEICE Electron. Express, 2007)

Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs. - Farhad Mehdipour; Hamid Noori; Morteza Saheb Zamani; Koji Inoue; Kazuaki J. Murakami (IEICE Trans. Inf. Syst., 2007)

Evaluation, prediction and reduction of routing congestion. - Mehdi Saeedi; Morteza Saheb Zamani; Ali Jahanian 001 (Microelectron. J., 2007)

Proposing an efficient method to estimate and reduce crosstalk after placement in VLSI circuits. - Arash Mehdizadeh; Morteza Saheb Zamani (AICCSA, 2008)

Design space exploration for a coarse grain accelerator. - Farhad Mehdipour; Hamid Noori; Morteza Saheb Zamani; Koji Inoue; Kazuaki J. Murakami (ASP-DAC, 2008)

Moving forward: A non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithms. - Mehdi Saeedi; Morteza Saheb Zamani; Mehdi Sedighi (ASP-DAC, 2008)

Evaluating the Metro-on-Chip Methodology to Improve the Congestion and Routability. - Ali Jahanian 001; Morteza Saheb Zamani; Mostafa Rezvani; Mehrdad Najibi (CSICC, 2008)

A Novel Crosstalk Estimator after Placement. - Arash Mehdizadeh; Morteza Saheb Zamani (CSICC, 2008)

A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits. - Ehsan K. Ardestani; Morteza Saheb Zamani; Mehdi Sedighi (DSD, 2008)

Performance and Timing Yield Enhancement using Highway-on-Chip Planning. - Ali Jahanian 001; Morteza Saheb Zamani (DSD, 2008)

Multi-Objective Statistical Yield Enhancement using Evolutionary Algorithm. - Minoo Mirsaeedi; Morteza Saheb Zamani; Mehdi Saeedi (DSD, 2008)

Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics. - Mehdi Saeedi; Naser MohammadZadeh; Mehdi Sedighi; Morteza Saheb Zamani (DSD, 2008)

An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty. - Morteza Saheb Zamani; Maryam Taajobian; Mehdi Saeedi (DSD, 2008)

FPGA-Based Circuit Model Emulation of Quantum Algorithms. - Mahdi Aminian; Mehdi Saeedi; Morteza Saheb Zamani; Mehdi Sedighi (ISVLSI, 2008)

Performance Improvement of Physical Retiming with Shortcut Insertion. - Adel Dokhanchi; Mostafa Rezvani; Ali Jahanian 001; Morteza Saheb Zamani (ISVLSI, 2008)

An Efficient Method to Estimate Crosstalk after Placement Incorporating a Reduction Scheme. - Arash Mehdizadeh; Morteza Saheb Zamani; Hosein Shafiei (ISVLSI, 2008)

Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement. - Minoo Mirsaeedi; Morteza Saheb Zamani; Mehdi Saeedi (ISVLSI, 2008)

Shared-PPRM: A Memory-Efficient Representation for Boolean Reversible Functions. - Yasaman Sanaee; Mehdi Saeedi; Morteza Saheb Zamani (ISVLSI, 2008)

Synthesis of reversible circuits using a moving forward strategy. - Mehdi Saeedi; Mehdi Sedighi; Morteza Saheb Zamani (IEICE Electron. Express, 2008)

A fast IP routing lookup architecture for multi-gigabit switching routers based on reconfigurable systems. - Hamid Fadishei; Mehdi Saeedi; Morteza Saheb Zamani (Microprocess. Microsystems, 2008)

Using metro-on-chip in physical design flow for congestion and routability improvement. - Ali Jahanian 001; Morteza Saheb Zamani (Microelectron. J., 2008)

An architecture framework for an adaptive extensible processor. - Hamid Noori; Farhad Mehdipour; Kazuaki J. Murakami; Koji Inoue; Morteza Saheb Zamani (J. Supercomput., 2008)

A tileable switch module architecture for homogeneous 3D FPGAs. - Seyyed Ahmad Razavi; Morteza Saheb Zamani; Kia Bazargan (3DIC, 2009)

A cycle-based synthesis algorithm for reversible logic. - Zahra Sasanian; Mehdi Saeedi; Mehdi Sedighi; Morteza Saheb Zamani (ASP-DAC, 2009)

Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network. - Naser MohammadZadeh; Minoo Mirsaeedi; Ali Jahanian 001; Morteza Saheb Zamani (DATE, 2009)

Improving Latency of Quantum Circuits by Gate Exchanging. - Naser MohammadZadeh; Morteza Saheb Zamani; Mehdi Sedighi (DSD, 2009)

Improved performance and yield with chip master planning design methodology. - Ali Jahanian 001; Morteza Saheb Zamani (ACM Great Lakes Symposium on VLSI, 2009)

Rule-based optimization of reversible circuits. - Mona Arabzadeh; Mehdi Saeedi; Morteza Saheb Zamani (ASP-DAC, 2010)

A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs. - Hassan Ebrahimi; Morteza Saheb Zamani; Hamid R. Zarandi (ASP-DAC, 2010)

A Switch Box Architecture to Mitigate Bridging and Short Faults in SRAM-Based FPGAs. - Hassan Ebrahimi; Morteza Saheb Zamani; Seyyed Ahmad Razavi (DFT, 2010)

Reduction of process variation effect on FPGAs using multiple configurations. - Delasa Aghamirzaie; Seyyed Ahmad Razavi; Morteza Saheb Zamani; Mahdi Nabiyouni (VLSI-SoC, 2010)

Early Buffer Planning with Congestion Control Using Buffer Requirement Map. - Ali Jahanian 001; Morteza Saheb Zamani (J. Circuits Syst. Comput., 2010)

Reversible circuit synthesis using a cycle-based approach. - Mehdi Saeedi; Morteza Saheb Zamani; Mehdi Sedighi; Zahra Sasanian (ACM J. Emerg. Technol. Comput. Syst., 2010)

Quantum physical synthesis: Improving physical design by netlist modifications. - Naser MohammadZadeh; Mehdi Sedighi; Morteza Saheb Zamani (Microelectron. J., 2010)

A library-based synthesis methodology for reversible logic. - Mehdi Saeedi; Mehdi Sedighi; Morteza Saheb Zamani (Microelectron. J., 2010)

TSV reduction in homogeneous 3D FPGAs by logic resource and input pad replication. - Seyyed Hasan Moallempour; Seyyed Ahmad Razavi; Morteza Saheb Zamani (3DIC, 2011)

VMAP: A Variation Map-Aware Placement Algorithm for Leakage Power Reduction in FPGAs. - Behzad Salami 001; Morteza Saheb Zamani; Ali Jahanian 001 (DSD, 2011)

Evaluation of FPGA routing architectures under process variation. - Fatemeh Sadat Pourhashemi; Morteza Saheb Zamani (ACM Great Lakes Symposium on VLSI, 2011)

Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology. - Ali Jahanian 001; Morteza Saheb Zamani; Hamid Safizadeh (Integr., 2011)

Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes. - Hassan Ebrahimi; Morteza Saheb Zamani; Hamid R. Zarandi (Microelectron. J., 2011)

Block-based quantum-logic synthesis. - Mehdi Saeedi; Mona Arabzadeh; Morteza Saheb Zamani; Mehdi Sedighi (Quantum Inf. Comput., 2011)

Auxiliary qubit selection: a physical synthesis technique for quantum circuits. - Naser MohammadZadeh; Morteza Saheb Zamani; Mehdi Sedighi (Quantum Inf. Process., 2011)

Hardware Acceleration of STON Algorithm for Comparing 3-D Structure of Proteins. - Somayeh Kashi; Morteza Saheb Zamani (DSD, 2012)

OWQS: One-Way Quantum Computation Simulator. - Eesa Nikahd; Mahboobeh Houshmand; Morteza Saheb Zamani; Mehdi Sedighi (DSD, 2012)

Timing yield improvement of FPGAs utilizing enhanced architectures and multiple configurations under process variation (abstract only). - Fatemeh Sadat Pourhashemi; Morteza Saheb Zamani (FPGA, 2012)

Improving bitstream compression by modifying FPGA architecture. - Seyyed Ahmad Razavi; Morteza Saheb Zamani (FPGA, 2013)

Depth-optimized reversible circuit synthesis. - Mona Arabzadeh; Morteza Saheb Zamani; Mehdi Sedighi; Mehdi Saeedi (Quantum Inf. Process., 2013)

A quantum physical design flow using ILP and graph drawing. - Maryam Yazdani; Morteza Saheb Zamani; Mehdi Sedighi (Quantum Inf. Process., 2013)

Decomposition of Diagonal Hermitian Quantum Gates Using Multiple-Controlled Pauli Z Gates. - Mahboobeh Houshmand; Morteza Saheb Zamani; Mehdi Sedighi; Mona Arabzadeh (ACM J. Emerg. Technol. Comput. Syst., 2014)

A study on the efficiency of hardware Trojan detection based on path-delay fingerprinting. - Arash Nejat; Seyed Mohammad Hossein Shekarian; Morteza Saheb Zamani (Microprocess. Microsystems, 2014)

Automatic translation of quantum circuits to optimized one-way quantum computation patterns. - Mahboobeh Houshmand; Morteza Saheb Zamani; Mehdi Sedighi; Mohammad Hossein Samavatian (Quantum Inf. Process., 2014)

Quantum circuit physical design methodology with emphasis on physical synthesis. - Naser MohammadZadeh; Morteza Saheb Zamani; Mehdi Sedighi (Quantum Inf. Process., 2014)

GA-based approach to find the stabilizers of a given sub-space. - Mahboobeh Houshmand; Morteza Saheb Zamani; Mehdi Sedighi; Monireh Houshmand (Genet. Program. Evolvable Mach., 2015)

A Trust-Driven Placement Approach: A New Perspective on Design for Hardware Trust. - Seyed Mohammad Hossein Shekarian; Morteza Saheb Zamani (J. Circuits Syst. Comput., 2015)

One-way quantum computer simulation. - Eesa Nikahd; Mahboobeh Houshmand; Morteza Saheb Zamani; Mehdi Sedighi (Microprocess. Microsystems, 2015)

Improving hardware Trojan detection by retiming. - Seyed Mohammad Hossein Shekarian; Morteza Saheb Zamani (Microprocess. Microsystems, 2015)

FogLight: an efficient matrix-based approach to construct metabolic pathways by search space reduction. - Mehrshad Khosraviani; Morteza Saheb Zamani; Gholamreza Bidkhori (Bioinform., 2016)

Quantum-Logic Synthesis of Hermitian Gates. - Mona Arabzadeh; Mahboobeh Houshmand; Mehdi Sedighi; Morteza Saheb Zamani (ACM J. Emerg. Technol. Comput. Syst., 2016)

Geometry-Based Optimization of One-Way Quantum Computation Measurement Patterns. - Maryam Eslamy; Mahboobeh Houshmand; Morteza Saheb Zamani; Mehdi Sedighi (CoRR, 2017)

Quantum Circuit Synthesis Targeting to Improve One-Way Quantum Computation Pattern Cost Metrics. - Mahboobeh Houshmand; Mehdi Sedighi; Morteza Saheb Zamani; Kourosh Marjoei (ACM J. Emerg. Technol. Comput. Syst., 2017)

Latch-Based Structure: A High Resolution and Self-Reference Technique for Hardware Trojan Detection. - Ghobad Zarrinchian; Morteza Saheb Zamani (IEEE Trans. Computers, 2017)

A graph-based approach to analyze flux-balanced pathways in metabolic networks. - Mona Arabzadeh; Morteza Saheb Zamani; Mehdi Sedighi; Sayed-Amir Marashi (Biosyst., 2018)

A system architecture for parallel analysis of flux-balanced metabolic pathways. - Mona Arabzadeh; Mehdi Sedighi; Morteza Saheb Zamani; Sayed-Amir Marashi (Comput. Biol. Chem., 2020)

Combinational Counters: A Low Overhead Approach to Address DPA Attacks. - Ghobad Zarrinchian; Morteza Saheb Zamani (J. Circuits Syst. Comput., 2020)

Aging Mitigation in FPGAs Considering Delay, Power, and Temperature. - Mohammad Hadi Mottaghi; Mehdi Sedighi; Morteza Saheb Zamani (IEEE Trans. Reliab., 2020)

Real-Time Activity Recognition and Intention Recognition Using a Vision-based Embedded System. - Sahar Darafsh; Saeed Shiry Ghidary; Morteza Saheb Zamani (CoRR, 2021)

FIFA: A Fully Invertible FPGA Architecture to Reduce BTI-Induced Aging Effects. - Mohammad Hadi Mottaghi; Mehdi Sedighi; Morteza Saheb Zamani (IEEE Trans. Computers, 2022)

Runtime hardware Trojan detection by reconfigurable monitoring circuits. - Reza Fani; Morteza Saheb Zamani (J. Supercomput., 2022)

Low-overhead code concatenation approaches for universal quantum computation. - Eesa Nikahd; Morteza Saheb Zamani; Mehdi Sedighi (Quantum Inf. Process., 2023)

An energy-efficient and accuracy-aware edge computing framework for heart arrhythmia detection: A joint model selection and task offloading approach. - Vahid Amini; Mahmoud Momtazpour; Morteza Saheb Zamani (J. Supercomput., 2023)

A parallel computing architecture based on cellular automata for hydraulic analysis of water distribution networks. - Ali Suvizi; Azim Farghadan; Morteza Saheb Zamani (J. Parallel Distributed Comput., 2023)

A parallel computational approach for energy-efficient hydraulic analysis of water distribution networks using learning automata. - Ali Suvizi; Ruhollah Ahmadi; Morteza Saheb Zamani; Mohammad Reza Meybodi (Sustain. Comput. Informatics Syst., 2025)

A Scalable Synthesis Algorithm for Reversible Functions. - Moein Sarvaghad-Moghaddam; Morteza Saheb Zamani; Mehdi Sedighi (CoRR, 2025)