A CORDIC Based Digital Hardware For Adaptive Exponential Integrate and Fire Neuron. - Moslem Heidarpour; Arash Ahmadi; Rashid Rashidzadeh (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Digital Implementation of a Biological-Plausible Model for Astrocyte Ca ^2+ Oscillations. - Moslem Heidarpur; Arash Ahmadi; Majid Ahmadi (IWANN (2), 2019)

CORDIC-SNN: On-FPGA STDP Learning With Izhikevich Neurons. - Moslem Heidarpur; Arash Ahmadi; Majid Ahmadi; Mostafa Rahimi Azghadi (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Time Step Impact on Performance and Accuracy of Izhikevich Neuron: Software Simulation and Hardware Implementation. - Moslem Heidarpur; Arash Ahmadi; Majid Ahmadi (ISCAS, 2020)

CORDIC-Astrocyte: Tripartite Glutamate-IP3-Ca2+ Interaction Dynamics on FPGA. - Moslem Heidarpur; Parvin Khosravifar; Arash Ahmadi; Majid Ahmadi (IEEE Trans. Biomed. Circuits Syst., 2020)

Spiking Neural Networks: Modification and Digital Implementation. - Moslem Heidarpur (2020)

An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation. - Moslem Heidarpur; Mitra Mirhassani (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Selective Input Sparsity in Spiking Neural Networks for Pattern Classification. - Alexander J. Leigh; Moslem Heidarpur; Mitra Mirhassani (ISCAS, 2022)

A Low-Resource Digital Implementation of the Fitzhugh-Nagumo Neuron. - Alexander J. Leigh; Moslem Heidarpur; Mitra Mirhassani (PRIME, 2022)

A High-Accuracy Digital Implementation of the Morris-Lecar Neuron With Variable Physiological Parameters. - Alexander J. Leigh; Moslem Heidarpur; Mitra Mirhassani (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Corrections to "An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FPGA Implementation". - Moslem Heidarpur; Mitra Mirhassani (IEEE Trans. Very Large Scale Integr. Syst., 2022)

An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic. - Madhan Thirumoorthi; Moslem Heidarpur; Mitra Mirhassani; Mohammed A. S. Khalid (IEEE Trans. Very Large Scale Integr. Syst., 2022)

High-Performance FPGA Implementation of Fully Connected Networks of SAM Neurons. - Edris Zaman Farsa; Moslem Heidarpur; Arash Ahmadi; Mitra Mirhassani (ISCAS, 2023)

Digital Hardware Implementations of Spiking Neural Networks With Selective Input Sparsity for Edge Inferences in Controlled Image Acquisition Environments. - Alexander J. Leigh; Moslem Heidarpur; Mitra Mirhassani (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Resource-Efficient and High-Accuracy CORDIC-Based Digital Implementation of the Hodgkin-Huxley Neuron. - Alexander J. Leigh; Moslem Heidarpur; Mitra Mirhassani (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Novel Formulations of M-Term Overlap-Free Karatsuba Binary Polynomial Multipliers and Their Hardware Implementations. - Madhan Thirumoorthi; Alexander J. Leigh; Moslem Heidarpur; Mohammed A. S. Khalid; Mitra Mirhassani (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A High Speed and Area Efficient Processor for Elliptic Curve Scalar Point Multiplication for GF(2m). - Madhan Thirumoorthi; Alexander J. Leigh; Moslem Heidarpur; Mitra Mirhassani; Mohammed A. S. Khalid (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A Novel and Efficient Large Integer Number Theoretic Transform Multiplier Based on Unified Blocks. - Shiva Nejati 002; Moslem Heidarpur; Mitra Mirhassani (LASCAS, 2025)

A Fully Pipelined FIFO Based Polynomial Multiplication Hardware Architecture Based On Number Theoretic Transform. - Moslem Heidarpur; Mitra Mirhassani; Norman Chang (CoRR, 2025)