Wire Sizing and Spacing for Lithographic Printability and Timing Optimization. - Ke Cao; Jiang Hu; Mosong Cheng (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A lithography-friendly structured ASIC design approach. - Salman Gopalani; Rajesh Garg; Sunil P. Khatri; Mosong Cheng (ACM Great Lakes Symposium on VLSI, 2008)