SHA-3 Instruction Set Extension for A 32-bit RISC processor architecture. - Ahmed S. Eissa; Mahmoud A. Elmohr; Mostafa A. Saleh; Khaled E. Ahmed; Mohammed M. Farag (ASAP, 2016)

Hardware implementation of a SHA-3 application-specific instruction set processor. - Mahmoud A. Elmohr; Mostafa A. Saleh; Ahmed S. Eissa; Khaled E. Ahmed; Mohammed M. Farag (ICM, 2016)