A Low Power CORDIC-Based Hardware Implementation of Izhikevich Neuron Model. - Abdelrahim Elnabawy; Hussien Abdelmohsen; Moatasem Moustafa; Mostafa Elbediwy; Amr Helmy; Hassan Mostafa (NEWCAS, 2018)

A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices. - Mostafa Elbediwy; Bill Pontikakis; Jean-Pierre David; Yvon Savaria (IEEE Access, 2023)

DR-PIFO: A Dynamic Ranking Packet Scheduler Using a Push-In-First-Out Queue. - Mostafa Elbediwy; Bill Pontikakis; Alireza Ghaffari; Jean-Pierre David; Yvon Savaria (IEEE Trans. Netw. Serv. Manag., 2024)