A 1.6 Gbyte/s data transfer rate 8 Mb embedded DRAM. - Shinji Miyano; Kenji Numata; Katsuhiko Sato; Tomoaki Yabe; Masaharu Wada; Ryo Haga; Motohiro Enkaku; Masazumi Shiochi; Yutaka Kawashima; Masayuki Iwase; Masahisa Ohgata; Junpei Kumagai; et al. (IEEE J. Solid State Circuits, 1995)

A DRAM module generator with an expandable cell array scheme. - Hideki Takeuchi; Tomoaki Yabe; Shinji Miyano; Takehiko Hojo; Motohiro Enkaku; Masaaki Yamada; Masami Murakata (CICC, 1998)

A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator. - Tomoaki Yabe; Shinji Miyano; Katsuhiko Sato; Masaharu Wada; Ryo Haga; Osamu Wada; Motohiro Enkaku; Takehiko Hojyo; Kenichiro Mimoto; Masaaki Tazawa; Tsutomu Ohkubo; Kenji Numata (IEEE J. Solid State Circuits, 1998)