Performance Measurement and Improvement of Asymmetric Three-Tr. Cell (ATC) DRAM toward 0.3V Memory Array Operation. - Motoi Ichihashi; Haruki Toda (VLSI Design, 2006)

Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond. - Koichiro Ishibashi; Tetsuya Fujimoto; Takahiro Yamashita; Hiroyuki Okada; Yukio Arima; Yasuyuki Hashimoto; Kohji Sakata; Isao Minematsu; Yasuo Itoh; Haruki Toda; Motoi Ichihashi; Yoshihide Komatsu; et al. (IEICE Trans. Electron., 2006)

An On-Chip Multi-Mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-Power Domain SoC Using a 65-nm Standard CMOS Logic Process. - Motoi Ichihashi; Hélène Lhermet; Edith Beigné; Frédéric Rothan; Marc Belleville; Amara Amara (J. Low Power Electron., 2010)

Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs. - Sandeep Kumar Samal; Deepak Nayak; Motoi Ichihashi; Srinivasa Banna; Sung Kyu Lim (ICCAD, 2016)

How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD Solutions. - Sandeep Kumar Samal; Deepak Nayak; Motoi Ichihashi; Srinivasa Banna; Sung Kyu Lim (ISLPED, 2016)

On the Design of Ultra-High Density 14nm Finfet Based Transistor-Level Monolithic 3D ICs. - Jiajun Shi; Deepak Nayak; Motoi Ichihashi; Srinivasa Banna; Csaba Andras Moritz (ISVLSI, 2016)

Sensitivity analysis for SoC performance benchmark against interconnect parasitic resistance and capacitance beyond 10-nm FinFET technology. - Motoi Ichihashi; Jia Zeng; Cole Zemke; Irene Lin; Greg Northrop; Ning Jin; Jongwook Kye (SoCC, 2016)

10T Differential-Signal SRAM Design in a L4-NM FinFET Technology for High-Speed Application. - Motoi Ichihashi; Youngtag Woo; Muhammed Ahosan Ul Karim; Vivek Joshi; David Burnett (SoCC, 2018)

Performance Boost Scheme with Activated Dummy Fin in 12-nm FinFET Technology for High-Performance Logic Application. - Motoi Ichihashi; Jia Zeng; Youngtag Woo; Xuelian Zhu; Chenchen Wang; James Mazza (ISQED, 2020)