Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors. - Jing Shen; Motoi Inaba; Koichi Tanno; Okihiko Ishizuka (ISMVL, 2000)

Realization of NMAX and NMIN Functions with Multi-Valued Voltage Comparators. - Motoi Inaba; Koichi Tanno; Okihiko Ishizuka (ISMVL, 2001)

Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits. - Motoi Inaba; Koichi Tanno; Okihiko Ishizuka (ISMVL, 2002)

Analog Inverter with Neuron-MOS Transistors and Its Application. - Motoi Inaba; Koichi Tanno; Okihiko Ishizuka (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Linear and Compact Floating Node Voltage-Controlled Variable Resistor Circuit. - Muneo Kushima; Motoi Inaba; Koichi Tanno (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Experiment Result of Down Literal Circuit and Analog Inverter on CMOS Double-Polysilicon Process. - Motoi Inaba (ISMVL, 2007)

Optimization of Current-Mode MVD-ORNS Arithmetic Circuits. - Motoi Inaba; Koichi Tanno; Ryota Sawada; Hisashi Tanaka; Hiroki Tamura (ISMVL, 2009)

Optimization and Verification of Current-Mode Multiple-Valued Digit ORNS Arithmetic Circuits. - Motoi Inaba; Koichi Tanno; Hiroki Tamura; Okihiko Ishizuka (IEICE Trans. Inf. Syst., 2010)