TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model. - Akihiro Takamura; Masashi Kuwako; Masashi Imai; Taro Fujii; Motokazu Ozawa; Izumi Fukasaku; Yoichiro Ueno; Takashi Nanya (ICCD, 1997)

TITAC-2: An Asynchronous 32-bit Microprocessor. - Akihiro Takamura; Motokazu Ozawa; Izumi Fukasaku; Taro Fujii; Yoichiro Ueno; Masashi Imai; Masashi Kuwako; Takashi Nanya (ASP-DAC, 1998)

Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. - Motokazu Ozawa; Masashi Imai; Hiroshi Nakamura; Takashi Nanya; Yoichiro Ueno (ASYNC, 2001)

Low-Power Design of 90-nm SuperH Processor Core. - Tetsuya Yamada; Masahide Abe; Yusuke Nitta; Kenji Ogura; Manabu Kusaoke; Makoto Ishikawa; Motokazu Ozawa; Kiwamu Takada; Fumio Arakawa; Osamu Nishii; Toshihiro Hattori (ICCD, 2005)

A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones. - Makoto Ishikawa; Tatsuya Kamei; Yuki Kondo; Masanao Yamaoka; Yasuhisa Shimazaki; Motokazu Ozawa; Saneaki Tamaki; Mikio Furuyama; Tadashi Hoshi; Fumio Arakawa; Osamu Nishii; Kenji Hirose; et al. (IEICE Trans. Electron., 2005)

SH-X: an embedded processor core for consumer appliances. - Fumio Arakawa; Makoto Ishikawa; Yuki Kondo; Tatsuya Kamei; Motokazu Ozawa; Osamu Nishii; Toshihiro Hattori (SIGARCH Comput. Archit. News, 2005)

Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core. - Tetsuya Yamada; Masahide Abe; Yusuke Nitta; Kenji Ogura; Manabu Kusaoke; Makoto Ishikawa; Motokazu Ozawa; Kiwamu Takada; Fumio Arakawa; Osamu Nishii; Toshihiro Hattori (IEICE Trans. Electron., 2006)

Development of processor cores for digital consumer appliances. - Fumio Arakawa; Tetsuya Yamada; Takashi Okada; Makoto Ishikawa; Yuki Kondo; Motokazu Ozawa; Tomoyuki Kodama; Osamu Nishii; Toshihiro Hattori; Tatsuya Kamei; Junichi Nishimoto; Shinichi Yoshioka (Syst. Comput. Jpn., 2006)