Logic circuits using resonant-tunneling hot-electron transistors (RHETs). - Motomu Takatsu; Kenichi Imamura; Hiroaki Ohnishi; Toshihiko Mori; Takami Adachihara; Shunichi Muto; Naoki Yokoyama (IEEE J. Solid State Circuits, 1992)

A CMOS multichannel 10-Gb/s transceiver. - Hideki Takauchi; Hirotaka Tamura; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Takaya Chiba; Hideaki Anbutsu; Hisakatsu Yamaguchi; Toshihiko Mori; Motomu Takatsu; Kohtaroh Gotoh; Toshiaki Sakai; et al. (IEEE J. Solid State Circuits, 2003)

Ising-Model Optimizer with Parallel-Trial Bit-Sieve Engine. - Satoshi Matsubara; Hirotaka Tamura; Motomu Takatsu; Danny Yoo; Behraz Vatankhahghadim; Hironobu Yamasaki; Toshiyuki Miyazawa; Sanroku Tsukamoto; Yasuhiro Watanabe; Kazuya Takemoto; Ali Sheikholeslami (CISIS, 2017)

Digital Annealer for High-Speed Solving of Combinatorial optimization Problems and Its Applications. - Satoshi Matsubara; Motomu Takatsu; Toshiyuki Miyazawa; Takayuki Shibasaki; Yasuhiro Watanabe; Kazuya Takemoto; Hirotaka Tamura (ASP-DAC, 2020)