A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. - Shigeki Ohbayashi; Makoto Yabuuchi; Koji Nii; Yasumasa Tsukamoto; Susumu Imaoka; Yuji Oda; Tsutomu Yoshihara; Motoshige Igarashi; Masahiko Takeuchi; Hiroshi Kawashima; Yasuo Yamaguchi; Kazuhiro Tsukamoto; et al. (IEEE J. Solid State Circuits, 2007)

A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology. - Masako Fujii; Koji Nii; Hiroshi Makino; Shigeki Ohbayashi; Motoshige Igarashi; Takeshi Kawamura; Miho Yokota; Nobuhiro Tsuda; Tomoaki Yoshizawa; Toshikazu Tsutsui; Naohiko Takeshita; Naofumi Murata; et al. (IEICE Trans. Electron., 2008)

A dynamic body-biased SRAM with asymmetric halo implant MOSFETs. - Makoto Yabuuchi; Yasumasa Tsukamoto; Hidehiro Fujiwara; Shigeki Tawa; Koji Maekawa; Motoshige Igarashi; Koji Nii (ISLPED, 2011)

A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology. - Kazuki Fukuoka; Ryo Mori; A. Kato; Motoshige Igarashi; Koji Shibutani; T. Yamaki; Shinji Tanaka; Koji Nii; Sadayuki Morita; Takao Koike; Noriaki Sakamoto (CICC, 2012)