A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme. - Mototsugu Hamada; Masafumi Takahashi; Hideho Arakida; Akihiko Chiba; Toshihiro Terazawa; Takashi Ishikawa; Masahiro Kanazawa; Mutsunori Igarashi; Kimiyoshi Usami; Tadahiro Kuroda (CICC, 1998)

Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques. - Kimiyoshi Usami; Mutsunori Igarashi; Takashi Ishikawa; Masahiro Kanazawa; Masafumi Takahashi; Mototsugu Hamada; Hideho Arakida; Toshihiro Terazawa; Tadahiro Kuroda (DAC, 1998)

A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. - Masafumi Takahashi; Mototsugu Hamada; Tsuyoshi Nishikawa; Hideho Arakida; Tetsuya Fujita; Fumitoshi Hatori; Shinji Mita; Kojiro Suzuki; Akihiko Chiba; Toshihiro Terazawa; Fumihiko Sano; Yoshinori Watanabe; et al. (IEEE J. Solid State Circuits, 1998)

Low-power CMOS digital design with dual embedded adaptive power supplies. - Tadahiro Kuroda; Mototsugu Hamada (IEEE J. Solid State Circuits, 2000)

A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM. - Masafumi Takahashi; Tsuyoshi Nishikawa; Mototsugu Hamada; Toshinari Takayanagi; Hideho Arakida; Noriaki Machida; Hideaki Yamamoto; Toshihide Fujiyoshi; Yoko Ohashi; Osamu Yamagishi; Tatsuo Samata; Atsushi Asano; et al. (IEEE J. Solid State Circuits, 2000)

Utilizing surplus timing for power reduction. - Mototsugu Hamada; Yukio Ootaguro; Tadahiro Kuroda (CICC, 2001)

A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI. - Mototsugu Hamada; Hiroyuki Hara; Tetsuya Fujita; Chen Kong Teh; Takayoshi Shimazawa; Naoyuki Kawabe; Takeshi Kitahara; Yu Kikuchi; Tsuyoshi Nishikawa; Makoto Takahashi; Yukihito Oowaki (CICC, 2005)

A phase noise minimization of CMOS VCOs over wide tuning range and large PVT variations. - Daisuke Miyashita; Hiroki Ishikuro; Shouhei Kousai; Hiroyuki Kobayashi; Hideaki Majima; Kenichi Agawa; Mototsugu Hamada (CICC, 2005)

A 1.2-V CMOS complex bandpass filter with a tunable center frequency. - Hideaki Majima; Hiroki Ishikuro; Kenichi Agawa; Mototsugu Hamada (ESSCIRC, 2005)

A 17-mW 0.66-mm2 direct-conversion receiver for 1-Mb/s cable replacement. - Shwetabh Verma; Junfeng Xu; Mototsugu Hamada; Thomas H. Lee (IEEE J. Solid State Circuits, 2005)

Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI. - Yukihito Oowaki; Shinichiro Shiratake; Toshihide Fujiyoshi; Mototsugu Hamada; Fumitoshi Hatori; Masami Murakata; Masafumi Takahashi (IEICE Trans. Electron., 2006)

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. - Toshihide Fujiyoshi; Shinichiro Shiratake; Shuou Nomura; Tsuyoshi Nishikawa; Yoshiyuki Kitasho; Hideho Arakida; Yuji Okuda; Yoshiro Tsuboi; Mototsugu Hamada; Hiroyuki Hara; Tetsuya Fujita; Fumitoshi Hatori; et al. (IEEE J. Solid State Circuits, 2006)

Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems. - Chen Kong Teh; Mototsugu Hamada; Tetsuya Fujita; Hiroyuki Hara; N. Ikumi; Yukihito Oowaki (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A -90 dBm sensitivity 0.13 μm CMOS bluetooth transceiver operating in wide temperature range. - Kenichi Agawa; Hideaki Majima; Hiroyuki Kobayashi; Masayuki Koizumi; Shin-ichiro Ishizuka; Takeshi Nagano; Makoto Arai; Yutaka Shimizu; Go Urakawa; Nobuyuki Itoh; Mototsugu Hamada; Nobuaki Otsuka (CICC, 2007)

A novel quality factor tuning scheme for active-RC filters. - Shouhei Kousai; Mototsugu Hamada; Rui Ito; Tetsuro Itakura (ESSCIRC, 2007)

An automated runtime power-gating scheme. - Mototsugu Hamada; Takeshi Kitahara; Naoyuki Kawabe; Hironori Sato; Tsuyoshi Nishikawa; Takayoshi Shimazawa; Takahiro Yamashita; Hiroyuki Hara; Yukihito Oowaki (ICCD, 2007)

WLAN/Bluetooth. - George Chien; Mototsugu Hamada (ISSCC, 2007)

A 19.7 MHz, Fifth-Order Active-RCChebyshev LPF for Draft IEEE802.11n With Automatic Quality-Factor Tuning Scheme. - Shouhei Kousai; Mototsugu Hamada; Rui Ito; Tetsuro Itakura (IEEE J. Solid State Circuits, 2007)

A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design. - Fumihiko Tachibana; Hironori Sato; Takahiro Yamashita; Hiroyuki Hara; Takeshi Kitahara; Shuou Nomura; Fumiyuki Yamane; Yoshiro Tsuboi; Keiko Seki; Shuuji Matsumoto; Yoshinori Watanabe; Mototsugu Hamada (CICC, 2008)

Architectures and Circuit Techniques for Nanoscale RF CMOS (Forum). - Stefan Heinen; Francesco Svelto; Jan Craninckx; Mototsugu Hamada; Domine Leenaerts; Chris Rudell (ISSCC, 2008)

A 1.2V 0.2-to-6.3GHz Transceiver with Less Than -29.5dB EVM@-3dBm and a Choke/Coil-Less Pre-Power Amplifier. - Shouhei Kousai; Daisuke Miyashita; Junji Wadatsumi; Asuka Maki; Takahiro Sekiguchi; Rui Ito; Mototsugu Hamada (ISSCC, 2008)

A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology. - Shuou Nomura; Fumihiko Tachibana; Tetsuya Fujita; Chen Kong Teh; Hiroyuki Usui; Fumiyuki Yamane; Yukimasa Miyamoto; Chaiyasit Kumtornkittikul; Hiroyuki Hara; Takahiro Yamashita; Jun Tanabe; Masaru Uchiyama; et al. (ISSCC, 2008)

RF-analog circuit design in scaled SoC. - Nobuyuki Itoh; Mototsugu Hamada (ASP-DAC, 2009)

A 0.6V 380µW -14dBm LO-input 2.4GHz double-balanced current-reusing single-gate CMOS mixer with cyclic passive combiner. - Jun Deguchi; Daisuke Miyashita; Mototsugu Hamada (ISSCC, 2009)

A 90nm CMOS CT BPF for Bluetooth transceivers with DT 1b-switched-resistor cutoff-frequency control. - Hideaki Majima; Mototsugu Hamada (ISSCC, 2009)

A Novel Automatic Quality Factor Tuning Scheme for a Low-Power Wideband Active-RC Filter. - Shouhei Kousai; Mototsugu Hamada; Rui Ito; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS. - Jun Deguchi; Daisuke Miyashita; Yosuke Ogasawara; Gaku Takemura; Masaomi Iwanaga; Kenichi Sami; Rui Ito; Junji Wadatsumi; Yuki Tsuda; Shoko Oda; Shunji Kawaguchi; Nobuyuki Itoh; et al. (ISSCC, 2010)

A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm. - Yu Kikuchi; Makoto Takahashi; Tomohisa Maeda; Hiroyuki Hara; Hideho Arakida; Hideaki Yamamoto; Yousuke Hagiwara; Tetsuya Fujita; Manabu Watanabe; Takayoshi Shimazawa; Yasuo Ohara; Takashi Miyamori; et al. (ISSCC, 2010)

A 0.13 µm CMOS Bluetooth EDR Transceiver with High Sensitivity over Wide Temperature Range and Immunity to Process Variation. - Kenichi Agawa; Shin-ichiro Ishizuka; Hideaki Majima; Hiroyuki Kobayashi; Masayuki Koizumi; Takeshi Nagano; Makoto Arai; Yutaka Shimizu; Asuka Maki; Go Urakawa; Tadashi Terada; Nobuyuki Itoh; et al. (IEICE Trans. Electron., 2010)

A Fully Integrated 2 ˟ 1 Dual-Band Direct-Conversion Mobile WiMAX Transceiver With Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifier in 65 nm CMOS. - Jun Deguchi; Daisuke Miyashita; Yosuke Ogasawara; Gaku Takemura; Masaomi Iwanaga; Kenichi Sami; Rui Ito; Junji Wadatsumi; Yuki Tsuda; Shoko Oda; Shunji Kawaguchi; Nobuyuki Itoh; et al. (IEEE J. Solid State Circuits, 2010)

An all-digital 8-DPSK polar transmitter with second-order approximation scheme and phase rotation-constant digital PA for bluetooth EDR in 65nm CMOS. - Hiroyuki Kobayashi; Shouhei Kousai; Yoshiaki Yoshihara; Mototsugu Hamada (ISSCC, 2011)

A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS. - Chen Kong Teh; Tetsuya Fujita; Hiroyuki Hara; Mototsugu Hamada (ISSCC, 2011)

A Low-Noise and Highly-Linear Transmitter with Envelope Injection Pre-Power Amplifier for Multi-Mode Radio. - Shouhei Kousai; Daisuke Miyashita; Junji Wadatsumi; Rui Ito; Takahiro Sekiguchi; Mototsugu Hamada; Kenichi Okada 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM. - Yu Kikuchi; Makoto Takahashi; Tomohisa Maeda; Masatoshi Fukuda; Yasuhiro Koshio; Hiroyuki Hara; Hideho Arakida; Hideaki Yamamoto; Yousuke Hagiwara; Tetsuya Fujita; Manabu Watanabe; Hirokazu Ezawa; et al. (IEEE J. Solid State Circuits, 2011)

A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter. - Daisuke Miyashita; Hiroyuki Kobayashi; Jun Deguchi; Shouhei Kousai; Mototsugu Hamada; Ryuichi Fujimoto (IEICE Trans. Electron., 2012)

4.1 A 3-phase digitally controlled DC-DC converter with 88% ripple reduced 1-cycle phase adding/dropping scheme and 28% power saving CT/DT hybrid current control. - Chen Kong Teh; Atsushi Suzuki; Manabu Yamada; Mototsugu Hamada; Yasuo Unekawa (ISSCC, 2014)

Deep learning application trial to lung cancer diagnosis for medical sensor systems. - Ryota Shimizu; Shusuke Yanagawa; Yasutaka Monde; Hiroki Yamagishi; Mototsugu Hamada; Toru Shimizu; Tadahiro Kuroda (ISOCC, 2016)

Convolutional neural network for industrial egg classification. - Ryota Shimizu; Shusuke Yanagawa; Toru Shimizu; Mototsugu Hamada; Tadahiro Kuroda (ISOCC, 2017)

Wireless power transfer to stacked modules for IoT sensor nodes. - Shusuke Yanagawa; Ryota Shimizu; Mototsugu Hamada; Toru Shimizu; Tadahiro Kuroda (ISOCC, 2017)

Balanced Mini-Batch Training for Imbalanced Image Data Classification with Neural Network. - Ryota Shimizu; Kosuke Asako; Hiroki Ojima; Shohei Morinaga; Mototsugu Hamada; Tadahiro Kuroda (AI4I, 2018)

Design Methodology in Wireless Power Transfer System for 3-D Stacked Multiple Receivers. - Shusuke Yanagawa; Ryota Shimizu; Mototsugu Hamada; Toru Shimizu; Tadahiro Kuroda (ISCAS, 2018)

QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS. - Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Junichiro Kadomoto; Tomoki Miyata; Mototsugu Hamada; Tadahiro Kuroda; Masato Motomura (ISSCC, 2018)

Comparative Performance Analysis of Dual-Rail Domino Logic and CMOS Logic Under NearThreshold Operation. - Tsuyoshi Maruyama; Mototsugu Hamada; Tadahiro Kuroda (MWSCAS, 2018)

Wireless Power Transfer System for 3-D stacked Multiple Receivers Switching between Single and Dual Frequency Modes. - Shusuke Yanagawa; Ryota Shimizu; Mototsugu Hamada; Tadahiro Kuroda (MWSCAS, 2018)

Fully Integrated OOK-Powered Pad-Less Deep Sub-Wavelength-Sized 5-GHz RFID with On-Chip Antenna Using Adiabatic Logic in 0.18μM CMOS. - Yuta Toeda; Takumi Fujimaki; Mototsugu Hamada; Tadahiro Kuroda (VLSI Circuits, 2018)

Optimization of Resonant Capacitance in Wireless Power Transfer System with 3-D Stacked Two Receivers. - Shusuke Yanagawa; Ryota Shimizu; Mototsugu Hamada; Toru Shimizu; Tadahiro Kuroda (IEICE Trans. Electron., 2018)

Live Demonstration: A Non-Contact Transmission Line Connector for USB3.1 HD-Video Streaming. - Tomoya Arakawa; Joshin Sone; Mitsuji Okada; Mototsugu Hamada; Tadahiro Kuroda (ISCAS, 2019)

Transmission Line Coupler: High-Speed Interface for Non-Contact Connecter. - Mototsugu Hamada; Tadahiro Kuroda (IEICE Trans. Electron., 2019)

QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS. - Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Mototsugu Hamada; Tadahiro Kuroda; Masato Motomura (IEEE J. Solid State Circuits, 2019)

A 50 Mbps/pin 12-input/output 40 nsec Latency Wireless Connector Using a Transmission Line Coupler with Compact SERDES IC in 180 nm CMOS. - Kohei Ando; Kazuhisa Akatsuka; Chaoran Cheng; Tomoya Arakawa; Kota Shiba; Mototsugu Hamada; Tadahiro Kuroda (ICECS, 2020)

A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. - Kota Shiba; Tatsuo Omori; Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Masato Motomura; Mototsugu Hamada; Tadahiro Kuroda (ISCAS, 2020)

Introduction to the Special Section on the 2019 Asian Solid-State Circuits Conference (A-SSCC). - Atsushi Kawasumi; Mototsugu Hamada; Po-Hung Chen (IEEE J. Solid State Circuits, 2020)

Sub-10-μm Coil Design for Multi-Hop Inductive Coupling Interface. - Tatsuo Omori; Kota Shiba; Mototsugu Hamada; Tadahiro Kuroda (ASP-DAC, 2021)

A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS. - Kota Shiba; Tatsuo Omori; Mototsugu Hamada; Tadahiro Kuroda (ASP-DAC, 2021)

A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna. - Saito Shibata; Reiji Miura; Yoshiki Sawabe; Kota Shiba; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (A-SSCC, 2021)

CA2 area detection from hippocampal microscope images using deep learning. - Shohei Morinaga; Tomoe Ishikawa; Masato Yasui; Mototsugu Hamada; Tadahiro Kuroda (MWSCAS, 2021)

A 16 nJ/Classification FPGA-Based Wired-Logic DNN Accelerator Using Fixed-Weight Non-Linear Neural Net. - Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS. - Kota Shiba; Tatsuo Omori; Kodai Ueyoshi; Shinya Takamaeda-Yamazaki; Masato Motomura; Mototsugu Hamada; Tadahiro Kuroda (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation. - Reiji Miura; Saito Shibata; Masahiro Usui; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (ASP-DAC, 2022)

A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network. - Yao-Chung Hsu; Atsutake Kosuge; Rei Sumikawa; Kota Shiba; Mototsugu Hamada; Tadahiro Kuroda (HCS, 2022)

A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers. - Kota Shiba; Mitsuji Okada; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (HCS, 2022)

A Low-power RFID with 100kbps Data Rate Employing High-speed Power Clock Generator for Complementary Pass-transistor Adiabatic Logic. - Saito Shibata; Yoshiki Sawabe; Kota Shiba; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (ICECS 2022, 2022)

A 7 Gb/s Micro Rotatable Transmission Line Coupler with Deep Proximity Coupling Mode and Ground Shielding Vias. - Ximing Wang; Atsutake Kosuge; Yasuhiro Hayashi; Mototsugu Hamada; Tadahiro Kuroda (ICECS 2022, 2022)

Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format. - Kota Shiba; Mitsuji Okada; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (NEWCAS, 2022)

An Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion Technique. - Lixing Yu; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (SAS, 2022)

A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System. - Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC. - Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2022)

A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using Convolutional Non-Linear Neural Network. - Atsutake Kosuge; Yao-Chung Hsu; Mototsugu Hamada; Tadahiro Kuroda (IEEE Open J. Circuits Syst., 2022)

mmWave-YOLO: A mmWave Imaging Radar-Based Real-Time Multiclass Object Recognition System for ADAS Applications. - Atsutake Kosuge; Satoshi Suehiro; Mototsugu Hamada; Tadahiro Kuroda (IEEE Trans. Instrum. Meas., 2022)

A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network. - Yao-Chung Hsu; Atsutake Kosuge; Rei Sumikawa; Kota Shiba; Mototsugu Hamada; Tadahiro Kuroda (ASP-DAC, 2023)

A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS. - Rei Sumikawa; Kota Shiba; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (ASP-DAC, 2023)

An Occlusion-Resilient mmWave Imaging Radar-Based Object Recognition System Using Synthetic Training Data Generation Technique. - Eitaro Kobayashi; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IECON, 2023)

A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network. - Dongzhu Li; Yao-Chung Hsu; Rei Sumikawa; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (ISCAS, 2023)

Analysis and Design of a 7 Gb/s Rotatable Non-contact Connector with Grid Array Package Application. - Ximing Wang; Atsutake Kosuge; Yasuhiro Hayashi; Kota Shiba; Mototsugu Hamada; Tadahiro Kuroda (NEWCAS, 2023)

A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application. - Atsutake Kosuge; Rei Sumikawa; Yao-Chung Hsu; Kota Shiba; Mototsugu Hamada; Tadahiro Kuroda (VLSI Technology and Circuits, 2023)

Guest Editorial Introduction to the Special Issue on the 2022 Symposium on VLSI Circuits. - Borivoje Nikolic; Mototsugu Hamada (IEEE J. Solid State Circuits, 2023)

A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver. - Kota Shiba; Mitsuji Okada; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2023)

A 10.7-µJ/Frame 88% Accuracy CIFAR-10 Single-Chip Neuromorphic Field-Programmable Gate Array Processor Featuring Various Nonlinear Functions of Dendrites in the Human Cerebrum. - Atsutake Kosuge; Yao-Chung Hsu; Rei Sumikawa; Mototsugu Hamada; Tadahiro Kuroda; Tomoe Ishikawa (IEEE Micro, 2023)

Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface. - Kota Shiba; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IEICE Trans. Electron., 2023)

Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS. - Kota Shiba; Mitsuji Okada; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 250.3μW Versatile Sound Feature Extractor Using 1024-point FFT 64-ch LogMel Filter in 40nm CMOS. - Akiho Kawada; Kenji Kobayashi; Jaewon Shin; Rei Sumikawa; Mototsugu Hamada; Atsutake Kosuge (APCCAS, 2024)

Efficient FPGA Resource Utilization in Wired-Logic Processors Using Coarse and Fine Segmentation of LUTs for Non-Linear Functions. - Dongzhu Li; Tianqi Zhao; Kenji Kobayashi; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (ISCAS, 2024)

A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA. - Dongzhu Li; Zhijie Zhan; Rei Sumikawa; Mototsugu Hamada; Atsutake Kosuge; Tadahiro Kuroda (IEICE Trans. Electron., 2024)

Introduction to the Special Issue on the 2023 Symposium on VLSI Circuits. - Mototsugu Hamada; Ron Kapusta (IEEE J. Solid State Circuits, 2024)

A Coarse- and Fine-Grained LUT Segmentation Method Enabling Single FPGA Implementation of Wired-Logic DNN Processor. - Yuxuan Pan; Dongzhu Li; Mototsugu Hamada; Atsutake Kosuge (ASP-DAC, 2025)

A 83.7% Resource Reduced FPGA-based Wired-Logic DNN Processor by Using Mixed-Precision Module Embedding Into Non-Linear Function LUT. - Yuxuan Pan; Mototsugu Hamada; Atsutake Kosuge (ISCAS, 2025)

13.6 A Via-Programmable DNN-Processor Fabrication Toward 1/40th Mask Cost. - Jaewon Shin; Rei Sumikawa; Dongzhu Li; Mototsugu Hamada; Atsutake Kosuge (ISSCC, 2025)

Analysis and Design of Coarse and Fine Segmented LUT Implementation for FPGA-Based Resource Efficient Wired-Logic DNN Processors. - Yuxuan Pan; Dongzhu Li; Mototsugu Hamada; Atsutake Kosuge (IEICE Trans. Electron., 2025)