The Implementation of the 65nm Dual-Core 64b Merom Processor. - Nabeel Sakran; Marcelo Yuffe; Moty Mehalel; Jack Doweck; Ernest Knoll; Avi Kovacs (ISSCC, 2007)

A fully integrated multi-CPU, GPU and memory controller 32nm processor. - Marcelo Yuffe; Ernest Knoll; Moty Mehalel; Joseph Shor; Tsvika Kurts (ISSCC, 2011)

An energy efficient 32nm 20 MB L3 cache for Intel® Xeon® processor E5 family. - Min Huang; Moty Mehalel; Ramesh Arvapalli; Songnian He (CICC, 2012)

A Fully Integrated Multi-CPU, Processor Graphics, and Memory Controller 32-nm Processor. - Marcelo Yuffe; Moty Mehalel; Ernest Knoll; Joseph Shor; Tsvika Kurts; Eran Altshuler; Eyal Fayneh; Kosta Luria; Michael Zelikson (IEEE J. Solid State Circuits, 2012)

An Energy Efficient 32-nm 20-MB Shared On-Die L3 Cache for Intel® Xeon® Processor E5 Family. - Min Huang; Moty Mehalel; Ramesh Arvapalli; Songnian He (IEEE J. Solid State Circuits, 2013)